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1. WO2009051120 - SUBSTRATE WITH SEMICONDUCTOR ELEMENT MOUNTED THEREON

Publication Number WO/2009/051120
Publication Date 23.04.2009
International Application No. PCT/JP2008/068609
International Filing Date 15.10.2008
IPC
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
H01L 23/14 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
14characterised by the material or its electrical properties
CPC
H01L 23/3735
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
373Cooling facilitated by selection of materials for the device ; or materials for thermal expansion adaptation, e.g. carbon
3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
H01L 23/49833
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49833the chip support structure consisting of a plurality of insulating substrates
H01L 23/5389
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
5389the chips being integrally enclosed by the interconnect and support structures
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H05K 1/0271
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
H05K 2203/1322
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2203Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
13Moulding and encapsulation; Deposition techniques; Protective layers
1305Moulding and encapsulation
1322Encapsulation comprising more than one layer
Applicants
  • 住友ベークライト株式会社 SUMITOMO BAKELITE COMPANY LIMITED [JP]/[JP] (AllExceptUS)
  • 杉野 光生 SUGINO, Mitsuo [JP]/[JP] (UsOnly)
  • 原 英貴 HARA, Hideki [JP]/[JP] (UsOnly)
  • 和布浦 徹 MEURA, Toru [JP]/[JP] (UsOnly)
Inventors
  • 杉野 光生 SUGINO, Mitsuo
  • 原 英貴 HARA, Hideki
  • 和布浦 徹 MEURA, Toru
Agents
  • 朝比 一夫 ASAHI, Kazuo
Priority Data
2007-26956916.10.2007JP
2008-26359110.10.2008JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SUBSTRATE WITH SEMICONDUCTOR ELEMENT MOUNTED THEREON
(FR) SUBSTRAT AVEC ÉLÉMENT SEMI-CONDUCTEUR MONTÉ SUR CELUI-CI
(JA) 半導体素子搭載基板
Abstract
(EN)
A substrate (10) with a semiconductor element mounted thereon is provided with a core substrate (1); a semiconductor element (2) mounted on one surface of the core substrate (1); a first layer (3) wherein the semiconductor element (2) is embedded; a second layer (4), which is arranged on the opposite side to the first layer (3) on the core substrate (1), and has the same materials and material composition ratios as those of the first layer (3); and at least one front layer (5) arranged on the first layer (3) and the second layer (4). The front layer (5) is harder than the first layer (3) and the second layer (4). The inequalities of 0.5≤X-Y≤13 are preferably satisfied, wherein X[GPa] is a Young's modulus of the front surface (5) at 25°C and Y[GPa] is a Young's modulus of the first layer (3) at 25°C.
(FR)
L'invention porte sur un substrat (10) avec un élément semi-conducteur monté sur celui-ci qui comporte un substrat central (1) ; un élément semi-conducteur (2) monté sur une surface du substrat central (1) ; une première couche (3) dans laquelle l'élément semi-conducteur (2) est incorporé ; une seconde couche (4), qui est agencée sur le côté opposé à la première couche (3) sur le substrat central (1), et a les mêmes matériaux et proportions de composition de matériau que ceux de la première couche (3) ; et au moins une couche avant (5) agencée sur la première couche (3) et la seconde couche (4). La couche avant (5) est plus dure que la première couche (3) et la seconde couche (4). Les inégalités 0,5 ≤ X-Y ≤ 13 sont de préférence satisfaites, dans lesquelles X[GPa] est un module de Young de la surface avant (5) à 25°C et Y[GPa] est un module de Young de la première couche (3) à 25°C.
(JA)
 半導体素子搭載基板10は、コア基板1と、コア基板1の一方の面に搭載された半導体素子2と、半導体素子2を埋め込む第1の層3と、コア基板1の第1の層3とは反対側に設けられ、第1の層3と材料およびその組成比率が同じである第2の層4と、第1の層3上および第2の層4上に設けられた少なくとも1層の表層5とを有し、表層5は、第1の層3および第2の層4よりも硬いことを特徴とする。表層5の25°Cにおけるヤング率をX[GPa]、第1の層3の25°Cにおけるヤング率をY[GPa]としたとき、0.5≦X-Y≦13の関係を満足するのが好ましい。
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