Processing

Please wait...

Settings

Settings

Goto Application

1. WO2009011977 - DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY

Publication Number WO/2009/011977
Publication Date 22.01.2009
International Application No. PCT/US2008/064969
International Filing Date 28.05.2008
IPC
G11C 16/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
CPC
G11C 11/41
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
G11C 29/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/021
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
021in voltage or current generators
G11C 29/028
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
028with adaption or trimming of parameters
G11C 5/147
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
147Voltage reference generators, voltage and current regulators
Applicants
  • FREESCALE SEMICONDUCTOR INC. [US]/[US] (AllExceptUS)
  • QURESHI, Qadeer, A. [US]/[US] (UsOnly)
  • DAVAR, Sushama [US]/[US] (UsOnly)
  • JEW, Thomas [US]/[US] (UsOnly)
Inventors
  • QURESHI, Qadeer, A.
  • DAVAR, Sushama
  • JEW, Thomas
Agents
  • KING, Robert, L.
Priority Data
11/777,63513.07.2007US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY
(FR) AJUSTEMENT DE TENSION DYNAMIQUE POUR UNE MÉMOIRE
Abstract
(EN)
A power supply voltage for a memory (14) on an integrated circuit (10) is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage (VDD1). A test memory (16) of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted (30), while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory (14) and test memory (16) may be physically implemented either separated or interspersed on the integrated circuit.
(FR)
L'invention concerne une tension d'alimentation électrique pour une mémoire (14) sur un circuit intégré (10) qui est ajustée de manière dynamique pendant le fonctionnement de la mémoire. Le fonctionnement de la mémoire comprend l'alimentation de la mémoire à une tension d'alimentation (VDD1). Une mémoire d'essai (16) du circuit intégré est alimentée simultanément tout en faisant fonctionner la mémoire. La mémoire d'essai et la mémoire comprennent chacune des cellules de bit d'un premier type de configuration de cellule de bit. Un niveau de tension de la tension d'alimentation est ajusté (30), tout en faisant fonctionner la mémoire, sur la base de l'essai de la mémoire d'essai. Le niveau de tension est ajusté avec des variations externes pour prendre une valeur qui garantit aucun dysfonctionnement de la mémoire mais minimise également avec précision la tension d'alimentation. Le système et le procédé peuvent être implémentés avec tout type de mémoire. La mémoire (14) et la mémoire d'essai (16) peuvent être physiquement implémentées de manière séparée ou entremêlée sur le circuit intégré.
Latest bibliographic data on file with the International Bureau