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1. WO2009009865 - MEMORY WITH DATA CONTROL

Publication Number WO/2009/009865
Publication Date 22.01.2009
International Application No. PCT/CA2008/001239
International Filing Date 07.07.2008
IPC
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 16/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
G11C 7/22 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write timing or clocking circuits; Read-write control signal generators or management
G11C 8/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
CPC
G11C 16/102
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
102External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
G11C 2207/107
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
10Aspects relating to interfaces of memory device to external buses
107Serial-parallel conversion of data or prefetch
G11C 2216/30
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2216Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
12Reading and writing aspects of erasable programmable read-only memories
30Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
G11C 7/1078
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
G11C 7/109
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
109Control signal input circuits
G11C 7/22
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
Applicants
  • MOSAID TECHNOLOGIES INCORPORATED [CA]/[CA]
Inventors
  • OH, HakJune
Agents
  • HAMMOND, Daniel
Priority Data
11/779,58718.07.2007US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY WITH DATA CONTROL
(FR) MÉMOIRE AVEC COMMANDE DE DONNÉES
Abstract
(EN)
In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured to input command strobe signals into the memory device that delineate command packets that are input into the memory device via the first data link. The second input is configured to input data strobe signals into the memory device that delineate data packets that are input into the memory device via the first data link. The first and second outputs are configured to output the command strobe signal and data strobe signal, respectively. The second data link is configured to output packets from the memory device.
(FR)
Dans un mode de réalisation selon l'invention, un dispositif données comprend une mémoire, une première liaison de données, une première entrée, une seconde entrée, une seconde liaison de données, une première sortie et une seconde sortie. La première liaison de données est configurée pour entrer un ou plusieurs paquets dans le dispositif mémoire. La première entrée est configurée pour entrer des signaux de transfert d'instruction dans le dispositif mémoire qui délimitent des paquets d'instruction qui sont mis en entrée dans le dispositif mémoire par l'intermédiaire de la première liaison de données. La seconde entrée est configurée pour entrer des signaux de transfert de données dans le dispositif données qui délimitent des paquets de données qui sont mis en entrée dans le dispositif mémoire par l'intermédiaire de la première liaison de données. Les première et seconde sorties sont configurées pour émettre le signal de transfert d'instruction et le signal de transfert de données, respectivement. La seconde liaison de données est configurée pour émettre des paquets provenant du dispositif mémoire.
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