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1. WO2009009639 - ELECTRONIC ASSEMBLIES WITHOUT SOLDER AND METHODS FOR THEIR MANUFACTURE

Publication Number WO/2009/009639
Publication Date 15.01.2009
International Application No. PCT/US2008/069600
International Filing Date 10.07.2008
Chapter 2 Demand Filed 10.07.2008
IPC
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H05K 3/32 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
30Assembling printed circuits with electric components, e.g. with resistor
32electrically connecting electric components or wires to printed circuits
CPC
H01L 2224/04105
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
H01L 2224/24195
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
24of an individual high density interconnect connector
241Disposition
24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
24153the body and the item being arranged next to each other, e.g. on a common substrate
24195the item being a discrete passive component
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/32245
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32245the item being metallic
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
Applicants
  • OCCAM PORTFOLIO LLC [US]/[US] (AllExceptUS)
  • FJELSTAD, Joseph C. [US]/[US] (UsOnly)
Inventors
  • FJELSTAD, Joseph C.
Agents
  • TICHANE, David
Priority Data
12/170,42609.07.2008US
60/959,14810.07.2007US
60/962,62731.07.2007US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ELECTRONIC ASSEMBLIES WITHOUT SOLDER AND METHODS FOR THEIR MANUFACTURE
(FR) ENSEMBLES ÉLECTRONIQUES DÉPOURVUS DE SOUDURES ET PROCÉDÉS DE FABRICATION DE CEUX-CI
Abstract
(EN)
A method for producing an assembly of electronic components and assemblies in accord with this, wherein the electronic components have component terminals. A conductive firmament having a first side and a second side is provided. Then the component terminals are connected to the first side of the firmament with an anisotropic conductor. A pattern is applied to the second side of said firmament. And portions of the firmament are removed based on the pattern, such that remaining portions of said firmament form the electrical circuit interconnecting the component terminals.
(FR)
Procédé de production d'un ensemble de composants électroniques et ensembles selon celui-ci, dans lequel les composants électroniques possèdent des bornes de composants. Un firmament conducteur ayant un premier côté et un second côté est prévu. Lorsque les bornes de composants sont reliées au premier côté du firmament avec un conducteur anisotrope, un motif est appliqué au second côté dudit firmament. Et des parties du firmament sont retirées sur la base du motif, afin que les parties restantes dudit firmament forment le circuit électrique reliant les bornes de composants.
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