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1. WO2009007335 - ARRANGEMENT OF SEMICONDUCTOR CHIPS IN A MULTILAYER FLOOR COVERING

Publication Number WO/2009/007335
Publication Date 15.01.2009
International Application No. PCT/EP2008/058747
International Filing Date 07.07.2008
Chapter 2 Demand Filed 13.05.2009
IPC
G08B 13/10 2006.01
GPHYSICS
08SIGNALLING
BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
13Burglar, theft or intruder alarms
02Mechanical actuation
10by pressure on floors, floor coverings, stair treads, counters, or tills
G08B 13/26 2006.01
GPHYSICS
08SIGNALLING
BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
13Burglar, theft or intruder alarms
22Electrical actuation
26by proximity of an intruder causing variation in capacitance or inductance of a circuit
G01L 1/14 2006.01
GPHYSICS
01MEASURING; TESTING
LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
1Measuring force or stress, in general
14by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators
H01H 3/14 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
3Mechanisms for operating contacts
02Operating parts, i.e. for operating driving mechanism by a mechanical force external to the switch
14adapted for operation by a part of the human body other than the hand, e.g. by foot
CPC
G08B 13/10
GPHYSICS
08SIGNALLING
BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
13Burglar, theft or intruder alarms
02Mechanical actuation
10by pressure on floors, floor coverings, stair treads, counters, or tills
Applicants
  • VORWERK & CO. INTERHOLDING GMBH [DE]/[DE] (AllExceptUS)
  • MEGGLE, Martin [DE]/[DE] (UsOnly)
  • WALLMEYER, Mario [DE]/[DE] (UsOnly)
Inventors
  • MEGGLE, Martin
  • WALLMEYER, Mario
Agents
  • MÜLLER, Enno
Priority Data
10 2007 031 964.010.07.2007DE
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) ANORDNUNG VON HALBLEITERCHIPS IN EINEM MEHRLAGIGEN BODENBELAG
(EN) ARRANGEMENT OF SEMICONDUCTOR CHIPS IN A MULTILAYER FLOOR COVERING
(FR) ARRANGEMENT DANS UN REVÊTEMENT DE SOL MULTICOUCHE
Abstract
(DE)
Die Erfindung betrifft eine Anordnung von mit Sensoren (7) verbundenen Chips (10) in einem mehrlagigen Bodenbelag. Um eine Anordnung der in Rede stehenden Art in herstellungstechnisch einfacher Weise weiter zu verbessern, wird vorgeschlagen, dass in einer ersten oberen Lage (1) in der Ebene distanzierte Leiterbahnen (4) ausgebildet sind zur Stromversorgung eines Chips (10), dass eine zweite mittlere Lage (2) vorgesehen ist, in der der Chip (10) angeordnet ist und dass eine dritte untere Lage (3) vorgesehen ist, welche ebenfalls leitend mit dem Chip (10) verbunden ist, wobei in den flächenmäßigen Zwischenräumen zwischen den Chips (10) Sensoren (7) angeordnet sind.
(EN)
The invention relates to an arrangement of chips (10) bonded with sensors (7) in a multilayer floor covering. In order further to improve an arrangement of the type under consideration herein, in a simpler way of technical production, the invention proposes that in a first upper layer (1) circuit paths (4) are formed, separated from each other in a plane, to provide power to a chip (10), that a second middle layer (2) is provided in which the chip (10) is located, and that a third lower layer (3) is provided which likewise is connected electrically to the chip (10), wherein sensors (7) are located in the surface gaps between the chips (10).
(FR)
L'invention concerne un arrangement de puces (10) reliées avec des capteurs (7) dans un revêtement de sol multicouche. Conformément à l'invention, pour améliorer facilement un arrangement du type concerné au niveau de la technique de fabrication, des pistes conductrices (4) espacées dans le plan destinées à alimenter électriquement une puce (10) sont réalisées dans une première couche supérieure (1) dans le plan, une deuxième couche centrale (2) est réalisée, dans laquelle est disposée la puce (10) et une troisième couche inférieure (3) est réalisée, laquelle est également reliée électriquement avec la puce (10). Selon l'invention, des capteurs (7) sont disposés dans les espaces intermédiaires en forme de surface entre les puces (10).
Also published as
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