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1. WO2009004870 - SEMICONDUCTOR PACKAGE

Publication Number WO/2009/004870
Publication Date 08.01.2009
International Application No. PCT/JP2008/059641
International Filing Date 26.05.2008
IPC
H01L 23/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
CPC
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 23/3114
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3107the device being completely enclosed
3114the device being a chip scale package, e.g. CSP
H01L 23/481
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
481Internal lead connections, e.g. via connections, feedthrough structures
H01L 24/05
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
H01L 24/13
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
H01L 24/29
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
Applicants
  • オリンパス株式会社 OLYMPUS CORPORATION [JP]/[JP] (AllExceptUS)
  • 小島 一哲 KOJIMA, Kazuaki [JP]/[JP] (UsOnly)
Inventors
  • 小島 一哲 KOJIMA, Kazuaki
Agents
  • 伊藤 進 ITOH, Susumu
Priority Data
2007-17771805.07.2007JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR PACKAGE
(FR) BOÎTIER DE SEMI-CONDUCTEUR
(JA) 半導体パッケージ
Abstract
(EN)
There is provided a semiconductor package of a chip size corresponding to a semiconductor element with a narrow electrode pad pitch. The semiconductor package (1) has a semiconductor substrate (10) having a first main surface (10A) and a second main surface (10B), a circuit element formed on the first main surface (10A), a plurality of electrode pads (20) connected to the circuit element provided on the first main surface (10A), a plurality of external connection terminals (70) provided on the second main surface (10B), one or more through holes (51) reaching the second main surface (10B) from the first main surface (10A), and a plurality of through wirings (60) each connecting a plurality of the electrode pads (20) with a plurality of the external connection terminals (70) through each of one or more through holes (51).
(FR)
La présente invention a trait à un boîtier de semi-conducteur de la taille d'une puce correspondant à un élément semi-conducteur doté d'un pas d'électrode étroit. Le boîtier de semi-conducteur (1) est équipé d'un substrat semi-conducteur (10) ayant une première surface principale (10A) et une seconde surface principale (10B), d'un élément de circuit formé sur la première surface principale (10A), d'une pluralité d'électrodes (20) connectées à l'élément de circuit disposé sur la première surface principale (10A), d'une pluralité de bornes de connexion extérieures (70) disposées sur la seconde surface principale (10B), d'un ou de plusieurs trous débouchants (51) atteignant la seconde surface principale (10B) depuis la première surface principale (10A), et d'une pluralité de câblages continus (60) connectant chacun une pluralité de pastilles d'électrodes (20) à une pluralité de bornes de connexion extérieures (70) à travers le ou chacun des trous débouchants (51).
(JA)
 電極パッドピッチが狭い半導体素子にも対応できるチップサイズの半導体パッケージを提供する。半導体パッケージ1は第1の主面10Aと第2の主面10Bを有する半導体基板10と、前記第1の主面10A上に形成された回路素子と、前記第1の主面10A上に設けられた前記回路素子と接続された複数の電極パッド20と、前記第2の主面10B上に設けられた複数の外部接続端子70と、前記第1の主面10Aから前記第2の主面10Bに到達する1以上の貫通孔51と、1以上の前記貫通孔51のそれぞれを通して前記複数の電極パッド20と前記複数の外部接続端子70とを、それぞれ接続する複数の貫通配線60を有する。
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