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Machine translation
1. (WO2008095283) SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH SYMMETRIC LOADS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2008/095283    International Application No.:    PCT/CA2008/000192
Publication Date: 14.08.2008 International Filing Date: 30.01.2008
Chapter 2 Demand Filed:    24.11.2008    
IPC:
H03K 5/13 (2006.01), H03L 7/085 (2006.01), H03L 7/089 (2006.01)
Applicants: MOSAID TECHNOLOGIES INCORPORATED [CA/CA]; 11 Hines Road, Kanata, Ontario K2K 2X1 (CA) (For All Designated States Except US)
Inventors: MAI, Tony; (CA)
Agent: SMART & BIGGAR; P.O. Box 2999, Station D, 900 - 55 Metcalfe Street, Ottawa, Ontario K1P 5Y6 (CA)
Priority Data:
11/703,634 08.02.2007 US
Title (EN) SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH SYMMETRIC LOADS
(FR) MONTAGE DE CIRCUITS DE POLARISATION SIMPLIFIES POUR ETAGE SEPARATEUR DIFFERENTIEL A CHARGES SYMETRIQUES
Abstract: front page image
(EN)A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P- type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbιas between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.
(FR)L'invention concerne un circuit de polarisation servant à polariser des circuits à retard différentiels. Le circuit selon l'invention est un circuit exempt de réaction constitué par un étage de sortie CMOS pourvu d'un transistor de type P et d'un transistor de type N, un transistor connecté à une diode étant situé entre le transistor de type P et le transistor de type N, l'étage de sortie recevant la tension de commande en entrée et produisant la Vnbιas entre le transistor de type P et le transistor connecté à la diode. Le circuit selon l'invention est plus simple que les circuits de polarisation classiques qui mettent en œuvre des amplificateurs à réaction et des amplificateurs opérationnels.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)