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Machine translation
1. (WO2008094968) CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2008/094968    International Application No.:    PCT/US2008/052405
Publication Date: 07.08.2008 International Filing Date: 30.01.2008
IPC:
G11C 8/16 (2006.01)
Applicants: ATMEL CORPORATION [US/US]; 2325 Orchard Parkway, San Jose, CA 95131 (US) (For All Designated States Except US).
VERGNES, Alain [FR/FR]; (FR) (For US Only).
MATULIK, Eric [FR/FR]; (FR) (For US Only).
SCHUMACHER, Frederic [FR/FR]; (FR) (For US Only)
Inventors: VERGNES, Alain; (FR).
MATULIK, Eric; (FR).
SCHUMACHER, Frederic; (FR)
Agent: STEFFEY, Charles, E.; Schwegman, Lundberg & Woessner, P.A., P.O. Box 2938, Minneapolis, MN 55402 (US)
Priority Data:
11/668,844 30.01.2007 US
Title (EN) CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER
(FR) CIRCUIT D'HORLOGE POUR CONTRÔLEUR DE MÉMOIRE DDR- DRAM SYNCHRONE
Abstract: front page image
(EN)A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.
(FR)Un circuit qui fournit un signal d'horloge retardé à un contrôleur de mémoire commandant un dispositif mémoire synchrone comprend un circuit de retard logique assurant un accès lecture au dispositif mémoire synchrone, lequel circuit de retard logique génère une information sur l'intervalle de retard. Une ligne retard programmable reçoit le signal d'horloge et l'information sur l'intervalle retour et retarde le signal d'horloge d'une valeur correspondant à l'intervalle de retard. Une porte OU exclusif 2 entrées reçoit à la fois le signal d'horloge et la sortie de la ligne retard programmable, une sortie OU exclusif fournissant le signal d'horloge 2X.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)