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Machine translation
1. (WO2008094797) DEVICE HAVING POCKETLESS REGIONS AND METHODS OF MAKING THE DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2008/094797    International Application No.:    PCT/US2008/051760
Publication Date: 07.08.2008 International Filing Date: 23.01.2008
IPC:
H01L 21/02 (2006.01)
Applicants: TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999, Dallas, TX 75265-5474 (US) (For All Designated States Except US).
BENAISSA, Kamel [DZ/US]; (US) (For US Only).
BALDWIN, Greg [US/US]; (US) (For US Only).
EKBOTE, Shashank [IN/US]; (US) (For US Only)
Inventors: BENAISSA, Kamel; (US).
BALDWIN, Greg; (US).
EKBOTE, Shashank; (US)
Agent: FRANZ, Warren, L.; Texas Instruments Incorporated, Deputy General Patent Counsel, P.O. Box 655474, MS 3999, Dallas, TX 75265-5474 (US)
Priority Data:
11/668,946 30.01.2007 US
Title (EN) DEVICE HAVING POCKETLESS REGIONS AND METHODS OF MAKING THE DEVICE
(FR) DISPOSITIF AYANT DES ZONES SANS POCHE ET PROCÉDÉ POUR FABRIQUER LE DISPOSITIF
Abstract: front page image
(EN)An integrated circuit has a first plurality of transistors (30) and a second plurality of transistors Each of the first plurality of transistors comprises a first gate structure (32) oriented in a first direction and each of the second plurality of transistors comprises a second gate structure oriented in a second direction Each of the first plurality of transistors is formed with at least one more pocket region than each of the second plurality of transistors Methods for forming the integrated circuit devices of the disclosure are also disclosed.
(FR)L'invention concerne un circuit intégré qui comporte une première pluralité de transistors (30) et une seconde pluralité de transistors. Chaque transistor de la première pluralité de transistors comprend une première structure de porte (32) orientée dans une première direction et chaque transistor de la seconde pluralité de transistors comprend une deuxième structure de porte orientée dans une seconde direction. Chaque transistor de la première pluralité de transistors est formé avec au moins une zone de poche de plus que chaque transistor de la seconde pluralité de transistors. L'invention décrit également des procédés pour former ces dispositifs de circuit intégré.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)