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1. WO2008082591 - HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY

Publication Number WO/2008/082591
Publication Date 10.07.2008
International Application No. PCT/US2007/026387
International Filing Date 28.12.2007
IPC
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
10
Programming or data input circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
34
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56
using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
06
Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/10 (2006.01)
G11C 16/34 (2006.01)
G11C 11/56 (2006.01)
G11C 5/06 (2006.01)
CPC
G11C 11/56
G11C 11/5628
G11C 11/5678
G11C 13/0004
G11C 13/0064
G11C 13/0069
Applicants
  • MARVELL WORLD TRADE LTD. [BB/BB]; L'Horizon Gunsite Road Brittons Hill, St. Michael, BB 14027, BB (AllExceptUS)
  • SUTARDJA, Pantas [US/US]; US (UsOnly)
Inventors
  • SUTARDJA, Pantas; US
Agents
  • BRENNAN, Michael, D. ; Harness, Dickey & Pierce, P.L.C. P.O. Box 828 Bloomfield Hills, MI 48303, US
Priority Data
60/883,15002.01.2007US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY
(FR) INTERFACE HAUTE VITESSE POUR UNE MÉMOIRE À MULTIPLES NIVEAUX
Abstract
(EN)
A solid state memory system comprises a first memory chip that includes a plurality of storage elements, and a controller. Each of the plurality of storage elements have a measurable parameter that varies between a lower limit and an upper limit. The controller receives write data, converts the write data to N target values, and transmits the N target values to the first memory chip. The first memory chip adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values, where N is an integer greater than zero.
(FR)
L'invention concerne un système mémoire semi-conducteur qui comprend une première puce mémoire comprenant une pluralité d'éléments de stockage et un contrôleur. Chacun de la pluralité d'éléments de stockage a un paramètre mesurable qui varie entre une limite inférieure et une limite supérieure. Le contrôleur reçoit des données d'écriture, convertit les données d'écriture en N valeurs cibles, et transmet les N valeurs cibles à la première puce mémoire. La première puce mémoire ajuste les paramètres mesurables correspondants des N éléments de stockage de la pluralité d'éléments de stockage aux N valeurs cibles, N étant un entier supérieur à zéro.
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