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1. WO2008048810 - PARTITIONED SOFT PROGRAMMING IN NON-VOLATILE MEMORY

Publication Number WO/2008/048810
Publication Date 24.04.2008
International Application No. PCT/US2007/080740
International Filing Date 08.10.2007
IPC
G11C 16/34 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 16/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
G11C 11/56 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
CPC
G11C 11/5628
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5628Programming or writing circuits; Data input circuits
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 16/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 16/3409
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
3409Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
G11C 16/3413
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
3413Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
G11C 16/3445
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3436Arrangements for verifying correct programming or erasure
344Arrangements for verifying correct erasure or for detecting overerased cells
3445Circuits or methods to verify correct erasure of nonvolatile memory cells
Applicants
  • SANDISK CORPORATION [US]/[US] (AllExceptUS)
  • ITO, Fumitoshi [JP]/[JP] (UsOnly)
Inventors
  • ITO, Fumitoshi
Agents
  • MAGEN, Burt
Priority Data
11/549,55313.10.2006US
11/549,56413.10.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PARTITIONED SOFT PROGRAMMING IN NON-VOLATILE MEMORY
(FR) PROGRAMMATION SOUPLE PARTITIONNÉE EN MÉMOIRE NON VOLATILE
Abstract
(EN)
Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed by soft programming portions of the set to provide more consistent soft programming rates and threshold voltages. A first soft programming pulse can be applied to a first group of cells of the set while inhibiting soft programming of a second group of cells. A second soft programming pulse can then be applied to the second group of cells while inhibiting soft programming of the first group of cells. A small positive voltage of lower magnitude than the soft programming pulses can be applied to the group of cells to be inhibited. The size of the small positive voltage can be chosen so that each memory cell of the set will experience similar capacitive coupling effects from neighboring transistors when it is undergoing soft programming.
(FR)
La présente invention concerne la programmation souple effectuée pour réduire la distribution de tensions seuils d'un ensemble de cellules de mémoire effacées. La programmation souple peut rapprocher la tension seuil de cellules de mémoire vers un niveau de vérification pour l'état d'effacement. Un ensemble de cellules de mémoire peut faire l'objet d'une programmation souple grâce à la programmation de parties de l'ensemble pour assurer des taux de programmation souple et de tensions seuils plus constants. Une première impulsion de programmation souple peut être appliquée à un premier groupe de cellules de l'ensemble tout en interdisant la programmation souple d'un second groupe de cellules. Une seconde impulsion de programmation souple peut ensuite être appliquée au second groupe de cellules tout en interdisant la programmation souple du premier groupe de cellules. Une tension positive faible de grandeur inférieure aux impulsions de programmation souple peut être appliquée au groupe de cellules à inhiber. La grandeur de la tension positive faible peut être choisie de sorte que chaque cellule de mémoire de l'ensemble va être soumise à des effets de couplage capacitif identiques à partir des transistors voisins lorsque la programmation souple lui est appliquée.
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