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1. WO2008022454 - SCALABLE MEMORY SYSTEM

Publication Number WO/2008/022454
Publication Date 28.02.2008
International Application No. PCT/CA2007/001469
International Filing Date 22.08.2007
IPC
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 5/14 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
G11C 8/18 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe or column address strobe signals
CPC
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 7/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/1042
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1015Read-write modes for single port memories, i.e. having either a random port or a serial port
1042using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
G11C 7/1072
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1072for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
G11C 7/1078
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
G11C 7/20
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
20Memory initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Applicants
  • MOSAID TECHNOLOGIES INCORPORATED [CA]/[CA] (AllExceptUS)
  • KIM, Jin-Ki [CA]/[CA] (UsOnly)
  • OH, HakJune [CA]/[CA] (UsOnly)
  • PYEON, Hong Beom [CA]/[CA] (UsOnly)
  • PRZYBYLSKI, Steven [CA]/[US] (UsOnly)
Inventors
  • KIM, Jin-Ki
  • OH, HakJune
  • PYEON, Hong Beom
  • PRZYBYLSKI, Steven
Agents
  • HUNG, Shin
Priority Data
11/840,69217.08.2007US
60/839,32922.08.2006US
60/868,77306.12.2006US
60/892,70502.03.2007US
60/902,00316.02.2007US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SCALABLE MEMORY SYSTEM
(FR) SYSTÈME DE MÉMOIRE ÉVOLUTIF
Abstract
(EN)
A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
(FR)
L'invention concerne une architecture de système de mémoire comprenant des dispositifs de mémoire montés en série. Ce système de mémoire est évolutif de manière à pouvoir comprendre un certain nombre de dispositifs de mémoire sans dégradation des performances, ni restructuration complexe. Chaque dispositif de mémoire comprend une interface série d'entrée/sortie pour communiquer avec d'autres dispositifs de mémoire et un contrôleur de mémoire. Ce contrôleur de mémoire émet des commandes dans au moins un flux binaire, ce flux binaire suivant un protocole de commande modulaire. Une commande comporte un code d'opération comprenant des informations d'adresse facultatives et une adresse de dispositif, de sorte que seul le dispositif de mémoire adressé réagisse à cette commande. Des signaux stroboscopiques de sortie de données et d'entrée de commande distincts sont fournis parallèlement à chaque flux de données de sortie et chaque flux de données de commande d'entrée respectivement, pour identifier le type de données et la longueur de ces données. Le protocole de commande modulaire est utilisé pour exécuter des opérations concurrentes dans chaque dispositif de mémoire afin d'améliorer davantage les performances.
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