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1. WO2007148856 - NAND FLASH MEMORY ARRAY HAVING PILLAR STRUCTURE AND FABRICATING METHOD OF THE SAME

Publication Number WO/2007/148856
Publication Date 27.12.2007
International Application No. PCT/KR2006/004635
International Filing Date 07.11.2006
Chapter 2 Demand Filed 15.12.2006
IPC
H01L 27/115 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
CPC
H01L 27/115
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
H01L 27/11521
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
H01L 27/11524
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
11524with cell select transistors, e.g. NAND
Applicants
  • SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATION [KR]/[KR] (AllExceptUS)
  • PARK, Byung Gook [KR]/[KR] (UsOnly)
  • CHO, Seong Jae [KR]/[KR] (UsOnly)
Inventors
  • PARK, Byung Gook
  • CHO, Seong Jae
Agents
  • KWON, O Jun
Priority Data
10-2006-005559620.06.2006KR
Publication Language English (EN)
Filing Language Korean (KO)
Designated States
Title
(EN) NAND FLASH MEMORY ARRAY HAVING PILLAR STRUCTURE AND FABRICATING METHOD OF THE SAME
(FR) RÉSEAU DE MÉMOIRE FLASH NON-ET À STRUCTURE EN PILIER, ET PROCÉDÉ DE FABRICATION CORRESPONDANT
Abstract
(EN)
The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. A NAND flash memory array of the present invention allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. A method for fabricating the NAND flash memory array having a pillar structure, which uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.
(FR)
La présente invention concerne un réseau de mémoire flash NON-ET à canaux verticaux et à structure de grille de paroi latérale ainsi qu'un procédé de fabrication correspondant. Le réseau de mémoire flash NON-ET de la présente invention comporte une structure de bande isolante et une ou plusieurs bandes semiconductrices bordent les deux côtés de la bande isolante. Le réseau de mémoire flash NON-ET de la présente invention permet l'amélioration de l'intégrité en diminuant la zone de cellule mémoire de moitié ou moins et il résout le problèmes de la structure tridimensionnelle conventionnelle de l'isolation entre non seulement les canaux mais aussi les régions de source/drain du fond des souilles. Un procédé de fabrication du réseau de mémoire flash NON-ET à structure en pilier, qui utilise le procédé CMOS conventionnel et un procédé de gravure à masques minimaux, permet de réduire les coûts.
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