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1. WO2007147826 - LAYOUT PROCESSING SYSTEM

Publication Number WO/2007/147826
Publication Date 27.12.2007
International Application No. PCT/EP2007/056091
International Filing Date 19.06.2007
IPC
G06F 17/50 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
50Computer-aided design
G03F 1/14 2006.01
GPHYSICS
03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
1Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
14Originals characterised by structural details, e.g. supports, cover layers, pellicle rings
G06F 17/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
10Complex mathematical operations
CPC
G06F 30/39
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
39Circuit design at the physical level
G06F 30/398
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
39Circuit design at the physical level
398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Applicants
  • SAGANTEC ISRAEL LTD (AllExceptUS)
  • ARKHIPOV, Alexandre Anatolievich [US]/[US] (UsOnly)
  • BELENKY, Yefim [US]/[US] (UsOnly)
  • BERKENS, Martinus Maria [NL]/[NL] (UsOnly)
  • KARKLIN, Linard [US]/[US] (UsOnly)
  • LAY, Kuang-Hao [CN]/[US] (UsOnly)
  • STROLENBERG, Christinus Werner Hubertus [NL]/[NL] (UsOnly)
  • WILLEKENS, Jeroen Pieter Frank [NL]/[NL] (UsOnly)
Inventors
  • ARKHIPOV, Alexandre Anatolievich
  • BELENKY, Yefim
  • BERKENS, Martinus Maria
  • KARKLIN, Linard
  • LAY, Kuang-Hao
  • STROLENBERG, Christinus Werner Hubertus
  • WILLEKENS, Jeroen Pieter Frank
Agents
  • DELTAPATENTS B.V.
Priority Data
60/816,11323.06.2006US
60/833,14125.07.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LAYOUT PROCESSING SYSTEM
(FR) SYSTÈME DE TRAITEMENT DE DISPOSITION
Abstract
(EN)
A layout processing system for adapting an integrated circuit layout having integrated circuit objects constituting an integrated circuit, to obtain a process corrected layout which is a representation of the integrated circuit layout substantially corrected for local process variations in a manufacturing process The layout processing system comprises an equation adapter module for adapting a set of equations to obtain an adapted set of equations. Each equation in the set of equations comprises a mathematical representation of a design rule applied to groups of integrated circuit objects. The equation adapter module adapts of the set of equations those equations associated with a local process value The local process values represent local discrepancies between an object of a printable circuit layout that is manufacture able by the manufacturing process and a corresponding object of a printed image layout resulting from applying the manufacturing process to the printable circuit layout.
(FR)
La présente invention concerne un système de traitement de disposition pour adapter une disposition de circuit intégré ayant des objets de circuit intégré constituant un circuit intégré, pour obtenir une disposition corrigée de traitement, une représentation de la disposition du circuit intégré étant sensiblement corrigée pour les variations de traitement local dans un procédé de fabrication. Le système de traitement de disposition comprend un module adaptateur d'équation pour adapter un ensemble d'équations afin d'obtenir un ensemble adapté d'équations. Chaque équation de l'ensemble d'équations comprend une représentation mathématique d'une règle de conception appliquée aux groupes d'objets de circuit intégré. Le module adaptateur d'équation adapte le jeu d'équations associées à une valeur de traitement local. Les valeurs de traitement local représentent les divergences locales entre un objet d'une disposition de circuit imprimable qui peut être fabriqué par le procédé de fabrication et un objet correspondant d'une disposition d'image imprimée naissant de l'application du procédé de fabrication sur la disposition du circuit imprimable.
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