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1. WO2007146734 - SELF ALIGNED GATE JFET STRUCTURE AND METHOD

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[ EN ]

What is claimed is:
1. A method for forming a self-aligned gate structure for a junction field effect transistor, the method comprising:
forming a first conductive layer on a semiconductor substrate;
depositing a first dielectric layer over the first conductive layer;
forming a mask over first and second regions of the first conductive layer, wherein the first region defines a source electrode region and the second region defines a drain electrode region;
etching the dielectric layer and the first conductive layer not covered by the mask to expose a portion of the semiconductor substrate;
removing the mask;
forming a second dielectric layer over at least the exposed semiconductor substrate, the source electrode region, and the drain electrode region;
etching the second dielectric layer to expose a selected portion of the
semiconductor substrate, wherein the second dielectric layer continues to cover the sidewalls of the source electrode region and the drain electrode region; and
forming a second conductive layer on the selected portion of the semiconductor substrate to define a gate electrode region between and insulated from the source electrode region and the drain electrode region.

2. The method of Claim 1 , wherein the second dielectric layer that covers the sidewalls of the source electrode region and the drain electrode region aligns the gate electrode region with the source and drain electrode regions.

3. The method of Claim 2, wherein the gate electrode region is further aligned with an active area that comprises a channel region and a gate region.

4. The method of Claim 1 , wherein the first conductive layer comprises one of polysilicon, refractive metal, or suicide.

5. The method of Claim 1 , further comprising depositing a nitride layer above the first dielectric layer prior to forming the mask.

6. The method of Claim 1 , further comprising:
diffusing dopants of a first conductivity type from the source electrode region into the semiconductor substrate to form a source region; and
diffusing dopants of the first conductivity type from the drain electrode region into the semiconductor substrate to form a drain region.

7. The method of Claim 1 , further comprising implanting dopants of a first conductivity type to form a channel region.

8. The method of Claim 1 , further comprising diffusing dopants of a second conductivity type from the gate electrode region into the semiconductor substrate to form a gate region.

9. The method of Claim 1 , further comprising etching portions of the second dielectric layer such that a surface of the gate electrode region is planar relative to surfaces of the source electrode region and the drain electrode region.

10. The method of Claim 1 , wherein the second conductive layer comprises one of polysilicon, refractive metal, or suicide.

11. The method of Claim 1 , wherein the first conductive layer comprises n-type conductivity and the second conductive layer comprises p-type conductivity.

12. The method of Claim 1 , wherein the first conductive layer comprises p-type conductivity and the second conductive layer comprises n-type conductivity.

13. A junction field effect transistor, comprising:
a source region of a first conductivity type formed in a semiconductor substrate; a drain region of the first conductivity type formed in the semiconductor substrate; a channel region of the first conductivity type formed in the semiconductor substrate between the source region and the drain region;
a gate region of a second conductivity type formed in the semiconductor substrate and abutting the channel region;
a source electrode region in ohmic contact with the source region and having at least one sidewall that is covered with a dielectric layer;
a drain electrode region in ohmic contact with the drain region and having at least one sidewall that is covered with a dielectric layer; and
a gate electrode region formed between and insulated from the source electrode region and the drain electrode region by the dielectric layer.

14. The junction field effect transistor of Claim 13, wherein the dielectric layer that covers the sidewalls of the source electrode region and the drain electrode region aligns the gate electrode region with the source and drain electrode regions.

15. The junction field effect transistor of Claim 14, wherein the gate electrode region is further aligned with an active area that comprises the channel region and the gate region.

16. The junction field effect transistor of Claim 13, wherein the source electrode region comprises one of polysilicon, refractive metal, or suicide.

17. The junction field effect transistor of Claim 13, wherein the drain electrode region comprises one of polysilicon, refractive metal, or suicide.

18. The junction field effect transistor of Claim 13, wherein the gate electrode region comprises one of polysilicon, refractive metal, or suicide.

19. The junction field effect transistor of Claim 13, wherein the first conductivity type comprises n-type conductivity and the second conductivity type comprises p-type conductivity.

20. The junction field effect transistor of Claim 13, wherein the first conductivity type comprises p-type conductivity and the second conductivity type comprises n-type conductivity.