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1. WO2007146734 - SELF ALIGNED GATE JFET STRUCTURE AND METHOD

Publication Number WO/2007/146734
Publication Date 21.12.2007
International Application No. PCT/US2007/070589
International Filing Date 07.06.2007
IPC
H01L 31/112 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
08in which radiation controls flow of current through the device, e.g. photoresistors
10characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
101Devices sensitive to infra-red, visible or ultra-violet radiation
112characterised by field-effect operation, e.g. junction field-effect photo- transistor
CPC
H01L 29/1066
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
10with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
1066Gate region of field-effect devices with PN junction gate
H01L 29/41775
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
417carrying the current to be rectified, amplified or switched
41725Source or drain electrodes for field effect devices
41775characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
H01L 29/66901
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66893with a PN junction gate, i.e. JFET
66901with a PN homojunction gate
H01L 29/808
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
80with field effect produced by a PN or other rectifying junction gate ; , i.e. potential-jump barrier
808with a PN junction gate ; , e.g. PN homojunction gate
Applicants
  • DSM SOLUTIONS, INC. [US]/[US] (AllExceptUS)
  • KAPOOR, Ashok, Kumar [US]/[US] (UsOnly)
Inventors
  • KAPOOR, Ashok, Kumar
Agents
  • BHAVSAR, Samir, A.
Priority Data
11/450,11209.06.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SELF ALIGNED GATE JFET STRUCTURE AND METHOD
(FR) STRUCTURE JFET À GÂCHETTE AUTO-ALIGNÉE ET PROCÉDÉ
Abstract
(EN)
A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or suicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielctric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
(FR)
La présente invention concerne un JFET intégré sur un substrat comportant au moins une couche semi-conductrice et comportant des contacts de source et de drain sur une zone active et constituée d'un premier polysilicium (ou d'autres conducteurs comme un métal réfringent ou un siliciure) et un contact de gâchette auto-aligné constitué d'un second polysilicium qui a été poli jusqu'à être de niveau avec la surface supérieure d'une couche diélectrique recouvrant le haut des contacts de source et de drain. La couche diélectrique comporte de préférence une couverture de nitrure servant d'arrêt de polissage. Dans certains modes de réalisation, le nitrure recouvre entièrement la couche diélectrique recouvrant les contacts de source et de drain ainsi que la zone d'oxyde de champ définissant une zone active dudit JFET. L'invention concerne également un mode de réalisation avec une zone de canal réalisée par croissance épitaxique sur la surface du substrat.
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