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1. WO2007145843 - BIDIRECTIONAL BUFFER WITH SLEW RATE CONTROL AND METHOD OF BIDIRECTIONALLY TRANSMITTING SIGNALS WITH SLEW RATE CONTROL

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

BIDIRECTIONAL BUFFER WITH SLEW RATE CONTROL AND METHOD OF BIDIRECTIONALLY TRANSMITTING SIGNALS WITH SLEW RATE CONTROL

FIELD OF THE INVENTION

[0001] The present invention relates to a bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control.

BACKGROUND

[0002] Bidirectional buffers are well known devices that allow the transmission of a signal through the buffer. There are many types of buffers, and various combinations of features. For buffers of the type described by the present invention, some conventional buffers are bidirectional, others are unidirectional; some conventional buffers have slew rate control, others do not.

[0003] As mentioned, certain bidirectional buffers also possess the ability to control the slew rate of the signal that is input thereto. Providing for slew rate control can allow one to maintain better overall control of the circuits, as changes in signal that has been buffered have more predictability.

[0004] Conventional bidirectional circuits that have slew rate control require, however, a directional control input in order to operate properly. While in certain
circumstances this works fine, in others it does not.

[0005] What is desired is a bidirectional buffer with slew rate control in at least one direction, as well as a method of bidirectionally transmitting signals with slew rate control in at least one direction.

SUMMARY OF THE INVENTION

[0006] The present invention is directed to bidirectional buffer with slew rate control in at least one direction.

[0007] The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects of the present invention will become readily apparent when reading the following detailed description taken in conjunction with the appended drawings in which:

[0009] Fig. 1 illustrates a block diagram of the buffer according to the present invention.

[00010] Fig. 2 illustrates a detailed circuit diagram of the buffer according to the present invention.

[00011] Figs. 3A-3C are timing diagrams of various signals input to, outfrom from, and created within the buffer according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS.

[00012] Fig. 1 illustrates a block diagram of the buffer 100 according to the present invention in the boxed out section. The buffer 100 is preferably an ASIC, and in one particular embodiment is a circuit that complies with the HDMI specification. With respect to the HDMI implementation, it is relevant that the buffer 100 operates at 3.3v voltage levels and that the signal, typically a IkHz signal, must have a rise time <250us and fall time <50us.

[00013] In one mode of operation, a 1 kHz signal, termed a forward signal herein, is input on the IN node, buffered within the buffer 100, and output as a slew rate controlled IkH signal on the OUT node. In another mode of operation, a reverse signal is input on the OUT node, buffered within the buffer 100, and then output onto the IN node. In the embodiment described herein this reverse signal is not slew rate controlled.

[00014] With respect to the circuit elements and blocks shown in Fig. 1, some bias must be applied to the "OUT" and "IN" nodes, which is done through resistors Rext,in and Rext,out, as shown. Further, the blocks labeled "IPU", "IPD" , and "Impedance Control" are blocks with multiple transistors that perform functions as described further herein.

[00015] The following general overview of the above referenced circuit will first be provided, in conjunction with reference to the timing diagrams in Fig. 3. Thereafter, a more detailed explanation with respect to the circuit diagram of Fig. 2 will be provided. This particular embodiment is described for a circuit that operates having a 3.3 volt supply voltage and on a IkHz signal, although it will be apparent that the present invention can be
implemented with other supply voltages and signals.

[00016] The following explanation is provided with respect to the forward signal at the transitions of that signal from high to low and low to high, which provide an
understanding of how the circuit works.

HIGH-* LOW Transition:

When the IkHz forward signal is "HIGH" on the buffer 100 the "IN" node is pulled to GND quickly. The "Impedance Control" block detects this, as well as, the "IPU" block. The "OUT" node that is being slew rate controlled needs this quick transition to GND offset. To do this the "Impedance Control" signal takes the gate of pass transistor Nl close to GND on the edge of the IkHz "HIGH" signal while "IPU" block sources current to keep the voltage on "OUT" at 3.3V. Now the IkHz forward signal is a steady state "HIGH" and the gate of Nl is slowly allowed to come back to its nominal voltage allowing current to flow through it to GND through the buffer 100 from "IPU" block creating a gradual HIGH-^LOW transition on the "OUT* node.

LOW-^HIGH Transition:

When the IkHz forward signal releases from its "HIGH" state on the buffer 100, the "IN" node is pulled "HIGH" via an external path which in this case is through the external resistor Rext,in. The "Impedance Control" block detects this, as well as the "IPD" block. This time however the "Impedance Control" block allows the gate of transistor Nl to drift slightly higher than nominal but for all intents and purposes transistor Nl is still "ON". While Nl is "ON" the "IPD" block sinks current to GND so that the "OUP' node is slew rate controlled, thus creating a gradual LOW-^HIGH transition on the "OUT" node.

[00017] The following explanation is provided with respect to the reverse signal. In this mode of operation, there is not slew rate control. As such, during times in which the lKhz forward signal does not exist, there is no forward signal (or one also look at this as the low state of the IkHz forward signal). At such times, the reverse signal on the OUT node may be either high or low. The OUT's state will be dictated elsewhere by external circuitry not pertaining to this invention; however, buffer 100 must allow this "high" or "low" signal to be seen on the IN node, preferably at all times.

[00018] Fig. 2 illustrates a detailed circuit diagram of the buffer according to the present invention. Certain of the transistors shown are for simply biasing purposes so they are initially described:

1) N2, N3 and Pl provide a current mirror to develop a bias on P2.

2) A current source into N4 generates a Vt which is divided by 2 via R3 and R2 to develop a Vt/2 bias on the gate of IPD.

3) Similar to (2) N5, N6 and P4 are used as a current mirror to develop a diode drop off of the 3.3V Supply which is resistively divided by R4 and R5 to generate a (3.3-Vt/2) bias on the gate of IPU.

4) Transistors N7-N10 take a current source and ratio it up by 5: 1, or even more preferably 10:1 so it can be used to bias the "OUP' node via P5 and P6. In a preferred embodiment, the value of this current source is set by the HDMI specification. The current source can be any value taking into account the MAX bus capacitance; which in the HDMI specifrication implementation is 1 SOOpF for a single CEC bus device. In a preferred
implementation according to the present invention, there is used an internal current source of 12uA, as well as a 10:1 ratio, to obtain the 12OuA value for the current source, per the HDMI specification. The operational description provided herein is similar to that for the forward and reverse signals. Given the further circuit detail, the description is more complex, but the functions are the same.

For the forward signal, the following description is provided.

HIGH-┬╗LOW Transition:

When the IkHz forward signal is "HIGH" on the buffer 100 the "IN" node is pulled to GND quickly. Cl "sees" this sudden transition and takes the voltage on P3 (originally at OV) below GND turning it on hard. This pulls all the current from P2 through P3 to GND so the gate of Nl is at GND isolating the "IN" and "OUT" nodes. This is the case only for a brief time as the RC time constant (R 1/Cl) gradually allows the gate of P3 to go back to OV and the gate of Nl to return back to it's nominal voltage of 1.8V. It is noted that while the gate of P3 being at GND does allow current to flow through it continually to GND but it is a very weak transistor so it can't sink all 2.2uA, therefore, the gate of Nl will still have a bias on it.

As the gate of Nl is slowly rising back to its nominal state C3 is "watching" the "OUT" node. As soon as it starts to get pulled down via the buffer 100, C3 pulls the gate of IPU down turning it on. This allows current to source through Nl through the buffer 100 to GND keeping the voltage up on "OUT". Again the RC time constant of C3/R5 gradually shuts off the IPU current source which allows a slow HIGH to LOW transition on the "OUT" node.

LOW-* HIGH Transition:

[00019]
When the IkHz forward signal releases from its "HIGH" state on the buffer 100, the "IN" node is pulled "HIGH" via an external resistor and the "OUT" via the internal current source. However, while this sequence of events is trying to occur, C2 is "watching" the "OUT" node, and as soon as it is pulled high (i.e. +40OmV transition), this is reflected on the gate of IPD so that it turns on and sinks some of the current that's trying to pull-up the "OUT" node. C2/R2 is a time constant as well so the gate of IPD gradually returns back to its normal state of Vt/2 which causes the "OUT" node to rise gradually as well.

1000201 For the reverse signal, the following description is provided. The OUT's state will be dictated elsewhere by external circuitry not pertaining to this invention;
however, it preferably should allow this "high" or "low" signal to be seen on the IN node at all times. In this case, the pass transistor Nl will remain "ON" since there is no forward signal on the IN node triggering the time constant Rl/Cl. Furthermore, the steady state signal on the OUT node will not trigger C3/R5 or C2/R2 so Ipu and Ipd will remain OFF; therefore, the voltage on the OUT node will be allowed to dictate the voltage on the IN node with regards to a logic "low" and "high" state.

Modifications and variations of the preferred embodiment will be readily apparent to those skilled in the art. For instance, bidirectional slew rate control can be added, which then requires a directional control signal. Other such variations are within the scope of the present invention as defined by the claims.