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1. WO2007142261 - POWER ELEMENT MOUNTING SUBSTRATE, METHOD FOR MANUFACTURING THE POWER ELEMENT MOUNTING SUBSTRATE, POWER ELEMENT MOUNTING UNIT, METHOD FOR MANUFACTURING THE POWER ELEMENT MOUNTING UNIT, AND POWER MODULE

Publication Number WO/2007/142261
Publication Date 13.12.2007
International Application No. PCT/JP2007/061446
International Filing Date 06.06.2007
IPC
H01L 23/13 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
H01L 23/36 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/40 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
40Mountings or securing means for detachable cooling or heating arrangements
CPC
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 23/3735
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
373Cooling facilitated by selection of materials for the device ; or materials for thermal expansion adaptation, e.g. carbon
3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
H01L 23/3736
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
373Cooling facilitated by selection of materials for the device ; or materials for thermal expansion adaptation, e.g. carbon
3736Metallic materials
H01L 23/473
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation ; ; Temperature sensing arrangements
46involving the transfer of heat by flowing fluids
473by flowing liquids
H01L 24/32
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
H05K 1/09
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
09Use of materials for the ; conductive, e.g. ; metallic pattern
Applicants
  • 三菱マテリアル株式会社 MITSUBISHI MATERIALS CORPORATION [JP]/[JP] (AllExceptUS)
  • 黒光 祥郎 KUROMITSU, Yoshirou [JP]/[JP] (UsOnly)
  • 石塚 博弥 ISHIZUKA, Hiroya [JP]/[JP] (UsOnly)
  • 宮田 博志 MIYATA, Hiroshi [JP]/[JP] (UsOnly)
  • 北原 丈嗣 KITAHARA, Takeshi [JP]/[JP] (UsOnly)
  • 殿村 宏史 TONOMURA, Hiroshi [JP]/[JP] (UsOnly)
Inventors
  • 黒光 祥郎 KUROMITSU, Yoshirou
  • 石塚 博弥 ISHIZUKA, Hiroya
  • 宮田 博志 MIYATA, Hiroshi
  • 北原 丈嗣 KITAHARA, Takeshi
  • 殿村 宏史 TONOMURA, Hiroshi
Agents
  • 志賀 正武 SHIGA, Masatake
Priority Data
2006-15712406.06.2006JP
2006-15712506.06.2006JP
2006-16983820.06.2006JP
2006-19146812.07.2006JP
2006-22411221.08.2006JP
2007-06164012.03.2007JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) POWER ELEMENT MOUNTING SUBSTRATE, METHOD FOR MANUFACTURING THE POWER ELEMENT MOUNTING SUBSTRATE, POWER ELEMENT MOUNTING UNIT, METHOD FOR MANUFACTURING THE POWER ELEMENT MOUNTING UNIT, AND POWER MODULE
(FR) SUBSTRAT DE MONTAGE D'ÉLÉMENT DE PUISSANCE ET SON PROCÉDÉ DE FABRICATION, UNITÉ DE MONTAGE D'ÉLÉMENT DE PUISSANCE ET SON PROCÉDÉ DE FABRICATION, ET MODULE DE PUISSANCE
(JA) パワー素子搭載用基板、その製造方法、パワー素子搭載用ユニット、その製造方法、およびパワーモジュール
Abstract
(EN)
In a power element mounting substrate, a circuit layer is brazed on the surface of a ceramic board, and a power element is bonded on the surface of the circuit layer with solder. The circuit layer is formed of an Al alloy having an average purity of 98.0wt% or more but not more than 99.9wt% over the entire layer, the concentration of Fe contained on the side brazed to the ceramic board is less than 0.1wt%, and the concentration of Fe contained on the surface opposite to the brazed surface is 0.1wt% or more.
(FR)
Selon l'invention, dans un substrat de montage d'élément de puissance, une couche de circuit et brasée sur la surface d'une carte en céramique et un élément de puissance est soudé sur la surface de la couche de circuit grâce à de la soudure. La couche de circuit est formée d'un alliage d'Al présentant une pureté moyenne de 98,0 % en poids ou plus mais qui ne dépasse pas 99,9 % en poids sur la totalité de la couche, la concentration de Fe contenu sur le côté brasé sur la carte en céramique est inférieure à 0,1 % en poids et la concentration de Fe contenu sur la surface opposée à la surface brasée est de 0,1 % en poids ou plus.
(JA)
 セラミックス板の表面に回路層がろう付けされてなり、この回路層の表面にパワー素子がはんだ接合されるパワー素子搭載用基板であって、前記回路層は、全体の平均純度が98.0wt%以上99.9wt%以下のAl合金により形成されるとともに、前記セラミックス板とのろう付け面側に含まれるFeの濃度が0.1wt%未満とされ、かつこのろう付け面と反対の表面側に含まれるFeの濃度が0.1wt%以上とされていることを特徴とするパワー素子搭載用基板。
Also published as
Latest bibliographic data on file with the International Bureau