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1. WO2007142172 - MULTI-LAYERED WIRING MANUFACTURING METHOD, MULTI-LAYERED WIRING STRUCTURE, AND MULTI-LAYERED WIRING MANUFACTURING APPARATUS

Publication Number WO/2007/142172
Publication Date 13.12.2007
International Application No. PCT/JP2007/061253
International Filing Date 29.05.2007
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 21/3065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
3065Plasma etching; Reactive-ion etching
H01L 21/316 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314Inorganic layers
316composed of oxides or glassy oxides or oxide-based glass
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
CPC
H01L 21/02126
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02109characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
02112characterised by the material of the layer
02123the material containing silicon
02126the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
H01L 21/76808
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76808involving intermediate temporary filling with material
H01L 21/76814
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76814post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
H01L 21/76835
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76835Combinations of two or more different dielectric layers having a low dielectric constant
H01L 23/53238
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
53204Conductive materials
53209based on metals, e.g. alloys, metal silicides
53228the principal metal being copper
53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
H01L 23/5329
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
5329Insulating materials
Applicants
  • 日本電気株式会社 NEC Corporation [JP]/[JP] (AllExceptUS)
  • 大竹浩人 OHTAKE, Hiroto [JP]/[JP] (UsOnly)
  • 多田宗弘 TADA, Munehiro [JP]/[JP] (UsOnly)
  • 田上政由 TAGAMI, Masayoshi [JP]/[JP] (UsOnly)
  • 林喜宏 HAYASHI, Yoshihiro [JP]/[JP] (UsOnly)
Inventors
  • 大竹浩人 OHTAKE, Hiroto
  • 多田宗弘 TADA, Munehiro
  • 田上政由 TAGAMI, Masayoshi
  • 林喜宏 HAYASHI, Yoshihiro
Agents
  • 池田憲保 IKEDA, Noriyasu
Priority Data
2006-16120409.06.2006JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) MULTI-LAYERED WIRING MANUFACTURING METHOD, MULTI-LAYERED WIRING STRUCTURE, AND MULTI-LAYERED WIRING MANUFACTURING APPARATUS
(FR) procédé de fabrication de câblage multicouche, structure DE CÂBLAGE MULTICOUCHE, et appareil DE FABRICATION DE CÂBLAGE MULTICOUCHE
(JA) 多層配線製造方法と多層配線構造と多層配線製造装置
Abstract
(EN)
Provided is a multi-layered wiring structure, in which there are laminated at least one circuit element formed in a semiconductor substrate or a semiconductor layer, and a plurality of unit wiring structures so formed on the semiconductor substrate or the semiconductor layer as are electrically connected with the aforementioned at least one circuit element, and having a wire and a via hole plug formed by filling a wiring groove and a via hole formed in an insulating film, with a metal wire. In this multi-layered wiring structure, the carbon/silicon ratio in an inter-wiring-layer low-dielectric-constant film is higher than the carbon/siliconratio in an inter-via-layer low-dielectric-constant film. In order to manufacture the multi-layered wiring structure, an overlying second SiOCH low-dielectric-constant film is worked, when it is grooved and stopped on an underlying first SiOCH low-dielectric-constant film, by using an end point detection according to an emission spectroscopy of a mixed gas plasma containing at least N2 and CHxFy.
(FR)
L'invention concerne une structure de câblage multicouche, dans laquelle on trouve stratifié au moins un élément de circuit formé dans un substrat semi-conducteur ou une couche semi-conductrice, et une pluralité de structures de câblage unitaire ainsi formées sur le substrat semi-conducteur ou la couche semi-conductrice qui sont connectées électriquement avec ledit ou lesdits éléments de circuit mentionnés ci-dessus, et possédant un fil et un bouchon à trou traversant constitué par remplissage d'une rainure de câblage et un trou traversant formé dans un film isolant, avec un fil de métal. Dans cette structure de câblage multicouche, le rapport carbone/silicium dans un film de faible constante diélectrique de couche de câblage intermédiaire est supérieur au rapport carbone/silicium dans un film de faible constante diélectrique de couche traversante intermédiaire. Pour fabriquer la structure de câblage multicouche, un second film de faible constante diélectrique SiOCH superposé est usiné, pour être rainuré et arrêté sur un premier film de faible constante diélectrique SiOCH sous-jacent, en utilisant une détection de point d'extrémité selon une spectroscopie d'émission d'un plasma de gaz mélangé contenant au moins N2 et CHxFy.
(JA)
 多層配線構造は、半導体基板又は半導体層に形成された少なくとも1つの回路素子と、前記少なくとも1つの回路素子に電気的に接続された状態で前記半導体基板上又は前記半導体層上に形成され、絶縁膜に形成される配線溝およびビア孔に金属配線を充填して形成された配線およびビア孔プラグを有する単位配線構造が複数積層される。この多層配線構造において、配線層間低誘電率膜中のカーボン/シリコン比がビア層間低誘電率膜中のカーボン/シリコン比に比べて大きい。この多層配線構造を製造するには、上層に位置する第2のSiOCH低誘電率膜を溝加工して前記下層に位置する第1のSiOCH低誘電率膜上で停止させる際、NとCHを少なくとも含む混合ガスプラズマの発光分光による終点検出を用いて加工する。
Also published as
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