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1. WO2007141112 - SYSTEM AND METHOD FOR SECURE BOOT ACROSS A PLURALITY OF PROCESSORS

Publication Number WO/2007/141112
Publication Date 13.12.2007
International Application No. PCT/EP2007/054575
International Filing Date 11.05.2007
IPC
G06F 21/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
CPC
G06F 15/177
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
177Initialisation or configuration control
G06F 21/575
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
57Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
575Secure boot
G06F 21/755
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71to assure secure computing or processing of information
75by inhibiting the analysis of circuitry or operation
755with measures against power attack
G06F 9/4405
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
4401Bootstrapping
4405Initialisation of multiprocessor systems
Applicants
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US]/[US] (AllExceptUS)
  • IBM UNITED KINGDOM LIMITED [GB]/[GB] (MG)
  • O'NIELL, Clark, McKerall [US]/[US] (UsOnly)
  • DEMENT, Jonathan, James [US]/[US] (UsOnly)
  • DALE, Jason, Nathaniel [US]/[US] (UsOnly)
  • SPANDIKOW, Christopher, John [US]/[US] (UsOnly)
Inventors
  • O'NIELL, Clark, McKerall
  • DEMENT, Jonathan, James
  • DALE, Jason, Nathaniel
  • SPANDIKOW, Christopher, John
Agents
  • SEKAR, Anita
Priority Data
11/423,34209.06.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM AND METHOD FOR SECURE BOOT ACROSS A PLURALITY OF PROCESSORS
(FR) SYSTÈME ET PROCÉDÉ D'AMORÇAGE SÉCURISÉ ENTRE UNE PLURALITÉ DE PROCESSEURS
Abstract
(EN)
A system and method for secure boot across a plurality of processors are provided. With the system and method, boot code is partitioned into a plurality of boot code partitions. Processors of a multiprocessor system are selected to be boot processors and are each provided with a boot code partition to execute in a predetermined boot code sequence. Each processor executes its boot code partition in accordance with the boot code sequence and signals to a next processor the successful and uncompromised execution of its boot code partition. If any of the processors does not signal successful completion and/or uncompromised execution of its boot code partition, the boot operation fails. The processors may be arranged, with regard to the boot operation, in a daisy chain, ring, or master/slave arrangement, for example.
(FR)
La présente invention concerne un système et un procédé d'amorçage sécurisé entre une pluralité de processeurs. Le système et le procédé permettent de diviser un code d'amorçage en une pluralité de partitions. Des processeurs d'un système multiprocesseur sont sélectionnés en tant que processeurs d'amorçage et reçoivent chacun une partition de code d'amorçage à exécuter dans une séquence de code d'amorçage préétablie. Chaque processeur exécute sa partition de code d'amorçage selon cette séquence et signale à un processeur suivant une exécution réussie et fiable de sa partition. Si l'un des processeurs ne signale pas une exécution réussie et fiable de sa partition de code d'amorçage, l'opération d'amorçage échoue. Les processeurs peuvent par exemple être disposés, par rapport à l'opération d'amorçage, en chaîne, en anneau ou en configuration maître/esclave.
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