Processing

Please wait...

PATENTSCOPE will be unavailable a few hours for maintenance reason on Saturday 31.10.2020 at 7:00 AM CET
Settings

Settings

Goto Application

1. WO2007140366 - TESTING COMPONENTS OF I/O PATHS OF AN INTEGRATED CIRCUIT

Publication Number WO/2007/140366
Publication Date 06.12.2007
International Application No. PCT/US2007/069884
International Filing Date 29.05.2007
IPC
G01R 31/26 2006.01
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26Testing of individual semiconductor devices
CPC
G01R 31/318572
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3185Reconfiguring for testing, e.g. LSSD, partitioning
318533using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
318572Input/Output interfaces
G01R 31/31858
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3185Reconfiguring for testing, e.g. LSSD, partitioning
318533using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
318577AC testing, e.g. current testing, burn-in
31858Delay testing
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US] (AllExceptUS)
  • ABRAHAM, Jais [IN]/[IN] (UsOnly)
  • GOEL, Rohit [IN]/[IN] (UsOnly)
Inventors
  • ABRAHAM, Jais
  • GOEL, Rohit
Agents
  • FRANZ, Warren, L.
Priority Data
11/308,93126.05.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TESTING COMPONENTS OF I/O PATHS OF AN INTEGRATED CIRCUIT
(FR) ESSAI DE COMPOSANTS DE TRAJETS D'ENTRÉE/SORTIE D'UN CIRCUIT INTÉGRÉ
Abstract
(EN)
Testing the components of I/O paths in an integrated circuit (190) at at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.
(FR)
L'invention concerne l'essai des composants de trajets d'entrée/sortie dans un circuit intégré (190) fonctionnant à vitesse normale (à savoir, la vitesse à laquelle le circuit intégré fonctionnerait en mode normal sans essai). Dans un mode de réalisation, des cellules de balayage périphériques de différents trajets sont connectées dans une chaîne de balayage, et chaque cellule essaie le composant correspondant (par ex., le tampon) par lancement de données à une première instance de temps et par réception du résultat des données à une seconde instance de temps, la durée entre la première et la seconde instance de temps correspondant à celle du fonctionnement à vitesse normale. Si les données sont reçues avec précision, le composant peut être amené à fonctionner avec précision à vitesse normale.
Latest bibliographic data on file with the International Bureau