Processing

Please wait...

Settings

Settings

Goto Application

1. WO2007138848 - BONDED WAFER MANUFACTURING METHOD

Publication Number WO/2007/138848
Publication Date 06.12.2007
International Application No. PCT/JP2007/059864
International Filing Date 14.05.2007
IPC
H01L 21/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/3065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
3065Plasma etching; Reactive-ion etching
H01L 21/762 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
76Making of isolation regions between components
762Dielectric regions
H01L 27/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
CPC
H01L 21/3065
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
302to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
3065Plasma etching; Reactive-ion etching
H01L 21/76254
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
7624using semiconductor on insulator [SOI] technology
76251using bonding techniques
76254with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Applicants
  • 信越半導体株式会社 Shin-Etsu Handotai Co., Ltd. [JP]/[JP] (AllExceptUS)
  • 添田 康嗣 SOETA, Yasutsugu [JP]/[JP] (UsOnly)
  • 能登 宣彦 NOTO, Nobuhiko [JP]/[JP] (UsOnly)
Inventors
  • 添田 康嗣 SOETA, Yasutsugu
  • 能登 宣彦 NOTO, Nobuhiko
Agents
  • 好宮 幹夫 YOSHIMIYA, Mikio
Priority Data
2006-14791529.05.2006JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) BONDED WAFER MANUFACTURING METHOD
(FR) Procédé de fabrication de plaquettes liées
(JA) 貼り合わせウエーハの製造方法
Abstract
(EN)
Provided is a bonded wafer manufacturing method employing an ion implanting delamination method. The bonded wafer manufacturing method includes at least a step of bonding a base wafer with a bond wafer having a micro bubble layer formed by ion implantation; a step of delaminating the wafers by having the micro bubble layer as a boundary; and a step of removing the periphery of a thin film formed on the base wafer by the delamination step. At least a thin film periphery removing step after the delamination step is performed by dry etching wherein an etching gas is supplied from a nozzle, and the dry etching is performed by adjusting the innerdiameter of the gas jetting port of the nozzle and an interval between the gas jetting port of the nozzle and the surface of the thin film. Thus, the bonded wafer manufacturing method, wherein the thin film periphery can be easily removed, a removal width can be obtained with excellent repeatability, and deterioration of thin film quality can be effectively prevented, is provided.
(FR)
La présente invention concerne un procédé de fabrication de plaquettes liées utilisant un procédé de délaminage à implantation ionique. Ledit procédé comprend au moins une étape consistant à lier une plaquette de base à une plaquette de liaison comportant une couche de microbulles formée par implantation ionique; une étape consistant à délaminer des plaquettes, la couche de microbulles constituant la limite; et une étape consistant à retirer la périphérie d'une couche mince formée sur la plaquette de base par l'étape de délaminage. Au moins une étape de retrait de la périphérie de la couche mince après l'étape de délaminage est effectuée pargravure à sec dans laquelle un gaz de gravure est alimenté à partir d'une buse, et la gravure à sec est pratiquée en ajustant le diamètre interne de l'orifice d'éjection de gaz de la buse et un intervalle entre ledit orifice et la surface de la couche mince. Ainsi, le procédé de fabrication de plaquettes liées dans lequel on peut facilement retirer la périphérie de la couche mince est proposé, une largeur de retrait peut être obtenue avec une excellente faculté de répétition et la dégradation de la qualité de la couche mince peut être efficacement évitée.
(JA)
 本発明は、少なくとも、ベースウエーハとイオン注入により形成された微小気泡層を有するボンドウエーハとを接合する工程と、前記微小気泡層を境界として剥離する工程と、前記剥離工程によりベースウエーハ上に形成された薄膜の周辺部を除去する工程を含むイオン注入剥離法により貼り合わせウエーハを製造する方法において、少なくとも、剥離工程後の薄膜周辺部除去工程を、ノズルからエッチングガスを供給して行うドライエッチングで行い、該ドライエッチングは、前記ノズルのガス噴出口の内径及び前記ノズルのガス噴出口と前記薄膜の表面との間隔を調整して行うことを特徴とする貼り合わせウエーハの製造方法である。これにより、薄膜周辺部除去工程において、薄膜周辺部の除去を簡便に行うことができるとともに、再現良く取代幅が得られ、かつ、薄膜の品質の低下を効果的に防ぐことができる貼り合わせウエーハの製造方法が提供される。
Latest bibliographic data on file with the International Bureau