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1. WO2007108983 - STRAINED SILICON WITH ELASTIC EDGE RELAXATION

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I claim:
1. A semiconductor device comprising at least one MOSFET, the semiconductor device comprising:
a substrate (10, 20) comprising silicon and having first and second walls of one or more trench structures (16, 18) extending partially into the substrate (10, 20), a substrate interface region extending between the first and second walls;
a first layer (22) comprising germanium on the substrate interface region, the first layer extending for a first spacing between the first and second wall;
a second layer (24) comprising silicon formed on the first layer, the second layer extending between the first and second walls; and
a gate dielectric layer (50) on the second layer (24) separating the second layer from a gate electrode (52) so that the second layer (24) provides at least a part of a channel of the MOSFET device, wherein a concentration of germanium in the first layer (22) is greater than a concentration of germanium in the second layer,
the semiconductor device further characterized in that:
the MOSFET device is an n-channel device, the first layer (22) has a thickness less than a first thickness at which misfit dislocations form in the first layer (22) due to a lattice mismatch between the first layer (22) and the substrate (20), and
the first layer (22) induces a strain in the substrate interface region and in the second layer (24) over a lateral extent between the first and second walls.

2. The device of claim 1, wherein the first layer (22) has a first lower interface lattice spacing matched with a substrate interface in-plane lattice spacing characteristic of the substrate interface region, and the second layer (24) has a second lower interface in-plane lattice spacing matched with a first layer upper interface in-plane lattice spacing
characteristic of an upper interface of the first layer.

3. The device of claim 1, wherein the lateral extents of the first layer (22) and the second layer (24) are defined by first and second walls of one or more shallow trench isolation structures (58, 60), each of the first and the second walls extending through the second layer (24) and the first layer (22) and the one or more shallow trench isolation structures (58, 60) comprising insulating material, the lateral extent of the first layer (22) extending between the first and second walls.

4. The device of claim 3' wherein the first layer (22) is non-uniformly partially relaxed over the lateral extent and the strain in the second layer (24) is non-uniform over an extent between the first and second shallow trench isolation structures (58, 60).

5. The device of claims 1 , 2, 3 or 4, wherein the lateral extent of the first layer (22) along the length axis or the width axis of the MOSFET is less than 200 nm.

6. The device of claims 1, 2, 3 or 4, wherein the germanium atomic fraction of the first layer (22) is 20% or more larger than the germanium atomic fraction of the second layer (24), the germanium atomic fraction of the first layer (22) is between about 20% and 100%, and the germanium atomic fraction of the second layer (24) is about 0%.

7. The device of claims 1, 2, 3 or 4, further comprising at least one p-channel MOS field effect transistor having a source region and a drain region, the source and drain regions adapted to apply compressive stress to the channel of the p-channel MOS field effect transistor.

8. The device of claim 7, wherein the source and drain regions comprise silicon germanium above and in contact with an unstrained surface within the substrate.

9. A method of manufacturing a semiconductor device, the method comprising:
forming a first layer (22) comprising germanium over a substrate (20), the first layer comprising germanium at a greater concentration than the substrate (20);
forming a second layer (24) comprising silicon over the first layer (22), the first layer (22) comprising germanium at a higher concentration than the second layer (24); and
forming a gate dielectric layer (50) and a gate (52) on the second layer (24) for a MOS field effect transistor,
. the method further characterized in that: the first layer (22) is formed to have compressive stress and to have a thickness smaller than a first thickness at which plastic deformation occurs in the first layer (22),
etching through the first layer (22) and the second layer (24) and into the substrate in a pattern that at least in part defines a channel of the MOS field effect transistor, the etching allowing the first layer (22) to expand laterally, thereby straining the second layer (24) between walls of one or more openings formed by the etching.

10. The method of claim 9, wherein the etching forms a trench that is subsequently filled with an insulator as part of a shallow trench isolation structure (58, 60).

11. The method of claim 9, wherein the etching strains the second layer (24) non-uniformly and over a lateral extent of the second layer (24) of 200 nm or smaller.

12. The method of claim 9, wherein the lateral extent of the second layer (24) is such that the first layer (22) transfers strain energy to an interface with the substrate (20) and to the second layer (24) during the etching.

13. The method of claim 9, wherein the first layer (22) is non-uniformly strained and is incompletely relaxed across a lateral extent of the pattern.

14. The method of claim 9, further comprising forming at least a second MOS field effect transistor having a source region and a drain region, the source and drain regions adapted to apply stress to the channel of the second MOS field effect transistor.

15. The method of claim 14, wherein the second MOS field effect transistor is a p-channel MOS field effect transistor and the source and drain regions apply compressive stress to the channel of the p-channel MOS field effect transistor.

16. The method of claim 14, wherein the source and drain regions are formed by etching openings to expose the substrate and epitaxially growing a semiconductor layer within the openings.

17. The method of claim 16, wherein the semiconductor layer is silicon germanium.

18. The method of claim 9, wherein the etching includes forming a mask layer (36) over an intermediate layer (40) that is compliant for at least a period of time to allow the first layer (22) to expand laterally in response to the etching used to form the one or more trenches.

19. The method of claim 18, wherein the intermediate layer (40) is an oxide that becomes compliant when heated.

20. The method of claims 9-18 or 19, wherein the germanium atomic fraction of the first layer (22) is 20% or more larger than the germanium atomic fraction of the second layer (24), the germanium atomic fraction of the first layer (22) is between about 20% and 100%, and the germanium atomic fraction of the second layer (24) is about 0%.