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1. (WO2007108983) STRAINED SILICON WITH ELASTIC EDGE RELAXATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/108983 International Application No.: PCT/US2007/006171
Publication Date: 27.09.2007 International Filing Date: 12.03.2007
Chapter 2 Demand Filed: 16.01.2008
IPC:
H01L 29/10 (2006.01) ,H01L 29/165 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
16
including, apart from doping materials or other impurities, only elements of the fourth group of the Periodic System in uncombined form
161
including two or more of the elements provided for in group H01L29/1688
165
in different semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
ACORN TECHNOLOGIES, INC. [US/US]; 330 Wilshire Boulevard, 2nd Floor Santa Monica, CA 90401, US (AllExceptUS)
CLIFTON, Paul, A. [GB/US]; US (UsOnly)
Inventors:
CLIFTON, Paul, A.; US
Agent:
WRIGHT, William, H. ; Hogan & Hartson L.L.P. 1999 Avenue of the Stars, Suite 1400 Los Angeles, CA 90067, US
Priority Data:
11/378,73017.03.2006US
Title (EN) STRAINED SILICON WITH ELASTIC EDGE RELAXATION
(FR) SILICIUM SOLLICITE AVEC RELACHEMENT ELASTIQUE DES BORDS
Abstract:
(EN) A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations.
(FR) La présente invention concerne une couche épitaxiale mince de couverture de SiGe amenée à croître sur un substrat de silicium pour présenter une contrainte de compression biaxiale dans le plan de croissance. Une couche épitaxiale mince de silicium est déposée sur la couche de SiGe, la couche de SiGe présentant une épaisseur inférieure à ses épaisseurs critiques. Des rainures peu profondes sont pratiquées par la suite sur les couches épitaxiales, de telle sorte que l'énergie de sollicitation est redistribuée et que la contrainte de compression dans la couche de SiGe est partiellement relâchée de manière élastique et un degré d'effort de traction est induit aux couches de silicium adjacentes. Le procédé pour l'induction de l'effort de traction dans une couche supérieure de silicium étant élastique par nature, il est possible d'obtenir la sollicitation souhaitée tout en évitant la formation de dislocations inadaptées.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080106356EP2002480CN101405865