Processing

Please wait...

Settings

Settings

Goto Application

1. WO2007097791 - POWER CONSERVATION VIA DRAM ACCESS

Publication Number WO/2007/097791
Publication Date 30.08.2007
International Application No. PCT/US2006/044129
International Filing Date 14.11.2006
IPC
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
CPC
G06F 12/0835
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
0815Cache consistency protocols
0831using a bus scheme, e.g. with bus monitoring or watching means
0835for main memory peripheral accesses (e.g. I/O or DMA)
G06F 12/0888
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0888using selective caching, e.g. bypass
G06F 13/28
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
28using burst mode transfer, e.g. direct memory access ; DMA; , cycle steal
G06F 2212/1028
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1028Power efficiency
Y02D 10/00
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
10Energy efficient computing, e.g. low power processors, power management or thermal management
Applicants
  • MONTALVO SYSTEMS, INC. [US]/[US] (AllExceptUS)
  • MOLL, Laurent, R. [FR]/[US] (UsOnly)
  • SONG, Seungyoon, Peter [US]/[US] (UsOnly)
  • GLASKOWSKY, Peter, N. [US]/[US] (UsOnly)
  • CHENG, Yu-Quin [US]/[US] (UsOnly)
Inventors
  • MOLL, Laurent, R.
  • SONG, Seungyoon, Peter
  • GLASKOWSKY, Peter, N.
  • CHENG, Yu-Quin
Agents
  • SAWYER, Joseph, A., Jr.
Priority Data
11/351,07009.02.2006US
11/559,13313.11.2006US
11/559,19213.11.2006US
60/736,63215.11.2005US
60/736,73615.11.2005US
60/761,22023.01.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) POWER CONSERVATION VIA DRAM ACCESS
(FR) ÉCONOMIE D'ÉNERGIE PAR RÉDUCTION DES ACCÈS DRAM
Abstract
(EN)
Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
(FR)
Selon l'invention, une économie d'énergie par réduction des accès DRAM est procurée par un tampon/minicache pouvant fonctionner au choix en mode normal ou mode tampon. En mode tampon, adopté lorsque les CPU commencent à fonctionner en basse puissance, des accès non cachables (tels que ceux générés par un dispositif DMA) correspondant à des plages spécifiées d'adresses physiques ou ayant des caractéristiques spécifiques des accès eux-mêmes, sont traités par le tampon/minicache au lieu de l'être par un contrôleur de mémoire et la DRAM. Le traitement par le tampon/minicache comprend l'allocation de lignes lorsque les références ne concordent pas et le retour des données cachées du tampon/minicache lorsque les références concordent. Les lignes sont remplacées dans le tampon/minicache en fonction d'une politique de remplacement parmi plusieurs, incluant l'arrêt du remplacement lorsqu'aucune ligne libre n'est disponible. En mode normal, adopté lorsque les CPU commencent à fonctionner en haute puissance, le tampon/minicache fonctionne comme un cache conventionnel et les accès non cachables n'y sont pas traités.
Also published as
Latest bibliographic data on file with the International Bureau