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1. WO2007097179 - METHOD FOR MANUFACTURING SOI SUBSTRATE

Publication Number WO/2007/097179
Publication Date 30.08.2007
International Application No. PCT/JP2007/051894
International Filing Date 05.02.2007
IPC
H01L 21/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/322 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
322to modify their internal properties, e.g. to produce internal imperfections
H01L 27/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
CPC
H01L 21/3226
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
322to modify their internal properties, e.g. to produce internal imperfections
3221of silicon bodies, e.g. for gettering
3226of silicon on insulator
H01L 21/76251
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
7624using semiconductor on insulator [SOI] technology
76251using bonding techniques
H01L 21/76256
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
7624using semiconductor on insulator [SOI] technology
76251using bonding techniques
76256using silicon etch back techniques, e.g. BESOI, ELTRAN
Applicants
  • 信越半導体株式会社 Shin-Etsu Handotai Co., Ltd. [JP]/[JP] (AllExceptUS)
  • 竹野 博 TAKENO, Hiroshi [JP]/[JP] (UsOnly)
  • 能登 宣彦 NOTO, Nobuhiko [JP]/[JP] (UsOnly)
Inventors
  • 竹野 博 TAKENO, Hiroshi
  • 能登 宣彦 NOTO, Nobuhiko
Agents
  • 好宮 幹夫 YOSHIMIYA, Mikio
Priority Data
2006-04412021.02.2006JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD FOR MANUFACTURING SOI SUBSTRATE
(FR) PROCEDE DE FABRICATION DE SUBSTRAT EN SILICIUM SUR ISOLANT
(JA) SOI基板の製造方法
Abstract
(EN)
This invention provides a method for manufacturing an SOI substrate, comprising applying a single crystal silicon substrate, into which at least arsenic or antimony as an active impurity has been introduced to form a high-concentration layer, to a high-concentration layer-free single crystal silicon substrate through a silicon oxide film, heat treating the assembly for bonding, and then thinning the high-concentration layer-formed single crystal silicon substrate to form an SOI substrate comprising an SOI layer provided on the silicon oxide film, the SOI layer having an arsenic or antimony-containing high-concentration buried diffusion layer, wherein the active impurity is introduced by ion implantation, the acceleration energy in the ion implantation is brought to not more than 130 keV, and the thickness of the SOI layer is brought to not less than 3 μm. According to the method for manufacturing an SOI substrate, an SOI substrate in which an excellent metal contamination gettering capability has been imparted to an SOI layer having a high-concentration-buried diffusion layer, can be efficiently manufactured with high productivity at low cost.
(FR)
La présente invention concerne un procédé de fabrication d'un substrat en silicium sur isolant, comprenant l'application d'un substrat en silicium monocristallin, dans lequel au moins de l'arsenic ou de l'antimoine en tant qu'impureté active a été introduit pour former une couche de concentration élevée, dans un substrat en silicium monocristallin sans couche de concentration élevée par l'intermédiaire d'un film en oxyde de silicium, le traitement thermique de l'ensemble pour une liaison, et ensuite l'amincissement du substrat en silicium monocristallin sous forme de couche de concentration élevée pour former un substrat en silicium sur isolant comprenant une couche en silicium sur isolant disposée sur le film d'oxyde de silicium, la couche en silicium sur isolant ayant une couche de diffusion enterrée de concentration élevée contenant de l'arsenic ou de l'antimoine, l'impureté active étant introduite par implantation ionique, l'énergie d'accélération dans l'implantation ionique n'excédant pas 130 keV, et l'épaisseur de la couche en silicium sur isolant n'étant pas inférieure à 3 μm. Selon le procédé de fabrication d'un substrat en silicium sur isolant, un substrat en silicium sur isolant dans lequel une excellente capacité à obtenir une contamination métallique a été conférée à une couche en silicium sur isolant ayant une couche de diffusion enterrée de concentration élevée, peut être fabriqué de manière efficace avec une productivité élevée à bas coût.
(JA)
 本発明では、少なくとも、活性不純物であるヒ素又はアンチモンを導入して高濃度層を形成した単結晶シリコン基板と、高濃度層を形成しない単結晶シリコン基板とを、シリコン酸化膜を介して貼り合わせ、結合熱処理を施した後、前記高濃度層を形成した単結晶シリコン基板を薄膜化することにより、前記シリコン酸化膜の上にヒ素又はアンチモンを含む高濃度埋め込み拡散層を有するSOI層を形成したSOI基板を製造する方法において、前記活性不純物の導入を、イオン注入法により、イオン注入時の加速エネルギーを130keV以下として行い、かつ、前記形成するSOI層の厚さを3μm以上とする。これにより、高濃度埋め込み拡散層を有するSOI層に金属汚染に対して優れたゲッタリング能力を付加したSOI基板を、生産性良く、低コストで効率的に製造することのできるSOI基板の製造方法を提供できる。
Also published as
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