WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2007094824) METHOD FOR DOUBLE-SIDED PROCESSING OF THIN FILM TRANSISTORS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/094824    International Application No.:    PCT/US2006/039831
Publication Date: 23.08.2007 International Filing Date: 11.10.2006
IPC:
H01L 21/00 (2006.01)
Applicants: WISCONSIN ALUMNI RESEARCH FOUNDATION [US/US]; Post Office Box 7365, Madison, Wisconsin 53707-7365 (US) (For All Designated States Except US).
YUAN, Hao-Chih [--/US]; (US) (For US Only).
WANG, Guogong [CN/US]; (US) (For US Only).
ERIKSSON, Mark A. [US/US]; (US) (For US Only).
EVANS, Paul G. [US/US]; (US) (For US Only).
LAGALLY, Max G. [US/US]; (US) (For US Only).
MA, Zhenqiang [CN/US]; (US) (For US Only)
Inventors: YUAN, Hao-Chih; (US).
WANG, Guogong; (US).
ERIKSSON, Mark A.; (US).
EVANS, Paul G.; (US).
LAGALLY, Max G.; (US).
MA, Zhenqiang; (US)
Agent: MANNING, Michelle; FOLEY & LARDNER LLP, 150 East Gilman Street, Post Office Box 1497, Madison, Wisconsin 53701-1497 (US)
Priority Data:
11/276,065 13.02.2006 US
Title (EN) METHOD FOR DOUBLE-SIDED PROCESSING OF THIN FILM TRANSISTORS
(FR) PROCÉDÉ DE TRAITEMENT DOUBLE FACE DE TRANSISTORS À COUCHE MINCE
Abstract: front page image
(EN)This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
(FR)La présente invention concerne des procédés servant à fabriquer des dispositifs électroniques à couche mince possédant des capacités de traitement à la fois avant et arrière. Ces procédés permettent de réaliser des étapes de traitement à haute température pendant le traitement aussi bien de l'avant que de l'arrière. Les procédés sont bien adaptés à la fabrication de transistors à effet de champ à gâchette arrière ou à double gâchette, de transistors bipolaires à double face, et de circuit intégrés tridimensionnels.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)