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1. WO2007090814 - PROCESS FOR FABRICATING A NANO WIRE - BASED VERTICAL TRANSISTOR STRUCTURE

Publication Number WO/2007/090814
Publication Date 16.08.2007
International Application No. PCT/EP2007/051076
International Filing Date 05.02.2007
IPC
H01L 29/786 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
H01L 51/05 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
05specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
H01L 29/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
CPC
B82Y 10/00
BPERFORMING OPERATIONS; TRANSPORTING
82NANOTECHNOLOGY
YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
10Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 29/0665
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0657characterised by the shape of the body
0665the shape of the body defining a nanostructure
H01L 29/0673
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0657characterised by the shape of the body
0665the shape of the body defining a nanostructure
0669Nanowires or nanotubes
0673oriented parallel to a substrate
H01L 29/0676
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0657characterised by the shape of the body
0665the shape of the body defining a nanostructure
0669Nanowires or nanotubes
0676oriented perpendicular or at an angle to a substrate
H01L 29/7827
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
7827Vertical transistors
H01L 29/78642
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
786Thin film transistors, ; i.e. transistors with a channel being at least partly a thin film
78642Vertical transistors
Applicants
  • ECOLE POLYTECHNIQUE [FR]/[FR] (AllExceptUS)
  • PRIBAT, Didier [FR]/[FR] (UsOnly)
  • COJOCARU, Costel-Sorin [RO]/[FR] (UsOnly)
Inventors
  • PRIBAT, Didier
  • COJOCARU, Costel-Sorin
Agents
  • ESSELIN, Sophie
Priority Data
060107407.02.2006FR
Publication Language French (FR)
Filing Language French (FR)
Designated States
Title
(EN) PROCESS FOR FABRICATING A NANO WIRE - BASED VERTICAL TRANSISTOR STRUCTURE
(FR) PROCEDE DE FABRICATION D'UNE STRUCTURE DE TRANSISTOR VERTICAL A BASE DE NANOFILS
Abstract
(EN)
The invention relates to a process for fabricating a vertical transistor structure comprising, on a substrate (10), a first conducting layer (11) for providing the source or drain electrode function and an upper conducting layer (17) for providing the drain or source electrode function, characterized in that it comprises the following steps: production of a membrane consisting of a stack of porous layers, including at least an insulating first layer (20), a conducting second layer (12) for providing the gate electrode function, and insulating upper layer (13'), on the surface of the substrate covered with the conducting first layer (11) for providing the drain or source electrode function, said porous layers having substantially stacked pores; production of filaments made of semiconductor material in at least some of the stacked pores of the porous layers; and production of the conducting upper layer providing the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.
(FR)
L'invention concerne un procédé de fabrication d'une structure de transistor vertical comportant sur un substrat (10), une première couche conductrice assurant la fonction d' électrode de source ou de drain (11 ), une couche conductrice supérieure assurant la fonction d'électrode de drain ou de source (17), caractérisé en ce qu'il comprend les étapes suivantes : la réalisation d'une membrane consistant en un empilement de couches poreuses comportant au moins une première couche isolante (20), une seconde couche conductrice (12) assurant la fonction d'électrode de grille et une couche isolante supérieure (13'), à la surface du substrat recouvert de la première couche conductrice (11 ) assurant la fonction d'électrode de drain ou de source, lesdites couches poreuses présentant des pores sensiblement empilés ; la réalisation de filaments en matériau semi-conducteur à l'intérieur d'au moins une partie des pores empilés des couches poreuses ; la réalisation de la couche conductrice supérieure assurant la fonction d'électrode de source ou de drain à la surface de l'empilement de couches poreuses remplies de filaments en matériau semi-conducteur.
Also published as
Latest bibliographic data on file with the International Bureau