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1. (WO2007089949) MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES AND METHODS FOR FABRICATING MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/089949    International Application No.:    PCT/US2007/003248
Publication Date: 09.08.2007 International Filing Date: 05.02.2007
IPC:
H01L 21/28 (2006.01), H01L 21/8247 (2006.01), H01L 29/792 (2006.01), H01L 27/115 (2006.01), H01L 29/423 (2006.01), H01L 29/788 (2006.01)
Applicants: SPANSION LLC [US/US]; 915 DeGuigne Drive, Mail Stop 250, P.O. Box 3453, Sunnyvale, CA 94088-3453 (US) (For All Designated States Except US).
LEE, Chungho [KP/US]; (US) (For US Only).
ZHENG, Wei [CN/US]; (US) (For US Only).
CHANG, Chi [US/US]; (US) (For US Only).
KIM, Unsoon [US/--]; (US) (For US Only).
KINOSHITA, Hiroyuki [US/--]; (US) (For US Only)
Inventors: LEE, Chungho; (US).
ZHENG, Wei; (US).
CHANG, Chi; (US).
KIM, Unsoon; (US).
KINOSHITA, Hiroyuki; (US)
Agent: FRITZ, Raymond E.; 915 DeGulgne Drive, Mail Stop 250, P.O. Box 3453, Sunnyvale, CA 94088-3453 (US)
Priority Data:
60/764,847 04.02.2006 US
Title (EN) MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES AND METHODS FOR FABRICATING MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES
(FR) CELLULES DE MÉMOIRE À NOEUDS DE STOCKAGE DE CHARGE DIVISÉS ET LEURS PROCÉDÉS DE FABRICATION
Abstract: front page image
(EN)Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench (64) and an adjacent second trench (64) in a semiconductor substrate (52), the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region (58) in the substrate and a second source/drain-region (58) in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier (62) in the substrate between the first source/drain region and the second source drain region and forming a first storage element (84) on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line (60) is formed in contact with the first storage element and the second storage element.
(FR)L'invention concerne des cellules de mémoire possédant des noeuds de stockage de charge divisés et leurs procédés de fabrication. Un procédé de cette invention consiste à former une première tranchée (64) et une seconde tranchée (64) adjacente dans un substrat à semi-conducteur (52), lesdites première et seconde tranchées définissant chacune une première paroi latérale et une seconde paroi latérale et formant une première région de source/drain (58) et une seconde région de source/drain (58) dans le substrat. Les première et seconde régions de source/drain (58) sont formées sensiblement sous les première et seconde tranchées dans le substrat à semi-conducteur. Par ailleurs, un procédé consiste à former une barrière (62) de pénétration de ligne de bit dans le substrat entre les première et seconde régions de drain/source et à former un premier élément de stockage (84) sur la première paroi latérale de la première tranchée et un second élément de stockage sur la seconde paroi latérale du second élément. Une ligne de mot (60) est formée en contact avec les premier et second éléments de stockage.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)