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1. WO2007089885 - PASSIVE IMPEDANCE EQUALIZATION OF HIGH SPEED SERIAL LINKS

Publication Number WO/2007/089885
Publication Date 09.08.2007
International Application No. PCT/US2007/002722
International Filing Date 31.01.2007
IPC
H05K 1/02 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
H05K 1/14 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
14Structural association of two or more printed circuits
H01L 23/66 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
66High-frequency adaptations
H01P 5/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
PWAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE
5Coupling devices of the waveguide type
02with invariable factor of coupling
CPC
H01L 2224/16
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
H01L 23/66
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for ; , e.g. in combination with batteries
64Impedance arrangements
66High-frequency adaptations
H01L 2924/01078
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
01Chemical elements
01078Platinum [Pt]
H01L 2924/10253
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
10Details of semiconductor or other solid state devices to be connected
102Material of the semiconductor or solid state bodies
1025Semiconducting materials
10251Elemental semiconductors, i.e. Group IV
10253Silicon [Si]
H01L 2924/15174
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
15Details of package parts other than the semiconductor or other solid state devices to be connected
151Die mounting substrate
1517Multilayer substrate
15172Fan-out arrangement of the internal vias
15174in different layers of the multilayer substrate
H01L 2924/15311
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
15Details of package parts other than the semiconductor or other solid state devices to be connected
151Die mounting substrate
153Connection portion
1531the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
15311being a ball array, e.g. BGA
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • BANERJEE, Gaurab [IN]/[US] (UsOnly)
  • MOONEY, Stephen [US]/[US] (UsOnly)
Inventors
  • BANERJEE, Gaurab
  • MOONEY, Stephen
Agents
  • RYDER, Douglas
Priority Data
11/343,78031.01.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PASSIVE IMPEDANCE EQUALIZATION OF HIGH SPEED SERIAL LINKS
(FR) EGALISATION DE L'IMPEDANCE PASSIVE DE LIAISONS SERIE HAUT DEBIT
Abstract
(EN)
A passive impedance equalization network (250,255,260,265) for high speed serial links is described. The impedance equalization network may include at least one stepped impedance transformer near points of impedance discontinuities (205,225,210,230). The impedance discontinuities may be at an interface connection between two circuit boards. The impedance discontinuities on a circuit board may be at a die-package interface and/or a package-board interface. The stepped impedance transformer may be formed in a package trace, a board trace or both. Forming the stepped impedance transformers in the traces requires no modification to existing package/board design methodology or technology. The stepped impedance transformers can provide impedance matching over a range of frequencies. To account for modeling errors in the design of the stepped impedance transformers integrated circuits transmitting data over the serial link may include active circuitry to select an output/input impedance for transmitters/receivers. Other embodiments are otherwise disclosed herein.
(FR)
Certains modes de réalisation de la présente invention concernent un réseau d'égalisation d'impédance passive destiné aux liaisons série haut débit. Le réseau d'égalisation d'impédance comprend au moins un transformateur d'impédance à pas à proximité des points de discontinuité d'impédance. Les discontinuités d'impédance peuvent être situées à une connexion d'interface entre deux circuits imprimés. Les discontinuités d'impédance d'un circuit imprimé peuvent être situées à une interface puce-boîtier et/ou une interface boîtier-carte. Le transformateur d'impédance à pas peut être formé dans une trace de boîtier, une trace de carte ou les deux. La formation de transformateurs d'impédance à pas dans les traces ne nécessite aucune modification de la méthodologie ou de la technologie existantes de conception de boîtier/carte. Les transformateurs d'impédance à pas peuvent fournir une correspondance d'impédance sur une gamme de fréquences. Afin de prendre en compte les erreurs de modélisation dans la conception de transformateurs d'impédance à pas les circuits intégrés transmettant les données sur la liaison série peuvent comprendre un circuit actif destiné à sélectionner une impédance de sortie/entrée pour les émetteurs/récepteurs. La présente invention concerne également d'autres modes de réalisation.
Also published as
GB815404
GB0815404.9
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