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1. WO2007087620 - LOW PROFILE SEMICONDUCTOR SYSTEM HAVING A PARTIAL-CAVITY SUBSTRATE

Publication Number WO/2007/087620
Publication Date 02.08.2007
International Application No. PCT/US2007/061088
International Filing Date 26.01.2007
IPC
H01L 23/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
CPC
H01L 2224/16145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16135the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
16145the bodies being stacked
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/45144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
45144Gold (Au) as principal constituent
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
H01L 2224/48465
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
484Connecting portions
48463the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
48465the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US] (AllExceptUS)
  • GERBER, Mark A. [US]/[US] (UsOnly)
  • WACHTLER, Kurt P. [US]/[US] (UsOnly)
  • CASTRO, Abraham M. [US]/[US] (UsOnly)
Inventors
  • GERBER, Mark A.
  • WACHTLER, Kurt P.
  • CASTRO, Abraham M.
Agents
  • FRANZ, Warren L.
Priority Data
11/376,39415.03.2006US
60/762,55026.01.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LOW PROFILE SEMICONDUCTOR SYSTEM HAVING A PARTIAL-CAVITY SUBSTRATE
(FR) DISPOSITIF A SEMI-CONDUCTEUR EXTRA-PLAT DOTE D'UN SUBSTRAT A CAVITE PARTIELLE
Abstract
(EN)
A system (100), which has an electrically insulating substrate (101) with a thickness, a first, and a second surface. Electrically conductive paths (110) extend through the insulating body from the first to the second surface and have exit ports (120) at the end of the conductive paths on the first and the second surface. A cavity (130) extends downwardly from the first surface to a depth less than the thickness; the bottoms of the cavity and the first substrate surface have contact pads (141). The substrate further has electrically conductive lines (150) between the first and the second surface and under the cavity, contacting the paths. The system includes a stack of semiconductor chips (160, 170) with bond pads; one chip is attached to the bottom of the cavity and one chip is electrically connected to substrate contact pads.
(FR)
La présente invention concerne un dispositif (100) comprenant un substrat électriquement isolant (101) ayant une épaisseur ainsi qu'une première et une seconde surface. Des chemins électriquement conducteurs (110) traversent le corps isolant de la première à la seconde surface et comportent des orifices de sortie (120) à l'extrémité des chemins conducteurs sur la première et la seconde surface. Une cavité (130) est formée en creux dans la première surface sur une profondeur inférieure à l'épaisseur, les fonds de la cavité et de la première surface du substrat comprenant des plots de contact (141). Le substrat comporte également des lignes conductrices (150) entre la première et la seconde surface et sous la cavité, en contact avec les chemins. Le dispositif comprend des puces à semi-conducteur superposées (160, 170) avec des aires de soudure, une puce étant reliée au fond de la cavité et une autre étant reliée aux plots de contact du substrat.
Also published as
Latest bibliographic data on file with the International Bureau