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1. (WO2007086008) TUNNELING TRANSISTOR WITH BARRIER
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/086008    International Application No.:    PCT/IB2007/050239
Publication Date: 02.08.2007 International Filing Date: 24.01.2007
IPC:
H01L 21/336 (2006.01), H01L 29/06 (2006.01), H01L 29/10 (2006.01), H01L 29/78 (2006.01)
Applicants: NXP B.V. [NL/NL]; High Tech Campus 60, NL-5656 AG Eindhoven (NL) (For All Designated States Except US).
HURKX, Godefridus [NL/NL]; (AT) (For US Only).
AGARWAL, Prabhat [DE/BE]; (AT) (For US Only)
Inventors: HURKX, Godefridus; (AT).
AGARWAL, Prabhat; (AT)
Agent: RÖGGLA, Harald; NXP Semiconductors Austria GmbH, Gutheil-Schoder-Gasse 8-12, A-1102 Vienna (AT)
Priority Data:
06100814.0 25.01.2006 EP
Title (EN) TUNNELING TRANSISTOR WITH BARRIER
(FR) TRANSISTOR DE TUNNELISATION AVEC BARRIERE
Abstract: front page image
(EN)The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.
(FR)La présente invention concerne un transistor (21) qui comprend une source (24) et un drain (29) ainsi qu'une région barrière (27) située entre la source et le drain. La région barrière est séparée de la source et du drain par des régions dopées de manière faible ou intrinsèque (26, 28) d'un matériau à semi-conducteurs. Des barrières potentielles sont formées sur les interfaces de la région barrière et des régions dopées de manière faible ou intrinsèque. Une électrode de grille (32) est prévue au voisinage des barrières potentielles, de telle sorte que la hauteur ou la largeur efficace des barrières potentielles peut être modulée en appliquant une tension appropriée à l'électrode de grille.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)