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1. (WO2007084925) METHOD AND APPARATUS FOR DEBUGGING A MULTICORE SYSTEM
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/084925    International Application No.:    PCT/US2007/060645
Publication Date: 26.07.2007 International Filing Date: 17.01.2007
IPC:
G06F 11/267 (2006.01)
Applicants: QUALCOMM INCORPORATED [US/US]; ATTN: INTERNATIONAL IP ADMINISTRATION, 5775 Morehouse Drive, San Diego, California 92121 (US) (For All Designated States Except US).
JOHN, Johnny Kallacheril [IN/US]; (US) (For US Only)
Inventors: JOHN, Johnny Kallacheril; (US)
Agent: OGROD, Gregory D.; ATTN: INTERNATIONAL IP ADMINISTRATION, 5775 Morehouse Drive, San Diego, Califonia 92121 (US)
Priority Data:
60/759,797 17.01.2006 US
11/360,240 22.02.2006 US
Title (EN) METHOD AND APPARATUS FOR DEBUGGING A MULTICORE SYSTEM
(FR) PROCÉDÉ ET APPAREIL DE DÉBOGAGE D’UN SYSTÈME MULTICOEUR
Abstract: front page image
(EN)Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating the stop. The other processing core receives the first hardware signal and stops operation. Both processing cores stop at approximately the same time based on the first hardware signal. Thereafter, the first or second processing core receives another software command to resume operation and generates a second hardware signal indicating resumption of operation. The other processing core receives the second hardware signal and resumes operation. Both processing cores resume at approximately the same time based on the second hardware signal. The first and second hardware signals may come from the same or different processing cores.
(FR)L'invention porte sur des techniques de débogage d’un système multicoeur à arrêt synchrone et reprise des capacités. Dans une exécution, l’appareil (par exemple un ASIC) comporte un premier et un deuxième coeur de traitement qui pendant le débogage reçoivent un ordre logiciel de s’arrêter et d’émettre un premier signal indiquant l’arrêt. L’autre coeur de traitement reçoit ce premier signal et s’arrête. Les deux cœurs s’arrêtent quasiment ensemble suite au premier signal. Le premier et le deuxième signal peuvent être émis ou non par le même coeur de traitement.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)