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1. (WO2007083587) SOI WAFER MANUFACTURING METHOD AND SOI WAFER
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2007/083587 International Application No.: PCT/JP2007/050391
Publication Date: 26.07.2007 International Filing Date: 15.01.2007
IPC:
H01L 21/02 (2006.01) ,H01L 21/20 (2006.01) ,H01L 21/205 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants: YAGI, Shinichiro[JP/JP]; JP (UsOnly)
Shin-Etsu Handotai Co., Ltd.[JP/JP]; 6-2, Ohtemachi 2-chome, Chiyoda-ku, Tokyo 1000004, JP (AllExceptUS)
Inventors: YAGI, Shinichiro; JP
Agent: YOSHIMIYA, Mikio; 1st Shitaya Bldg. 8F 6-11, Ueno 7-chome, Taito-ku Tokyo 1100005, JP
Priority Data:
2006-01355823.01.2006JP
Title (EN) SOI WAFER MANUFACTURING METHOD AND SOI WAFER
(FR) PROCÉDÉ DE FABRICATION D’UNE PLAQUETTE EN SILICIUM SUR ISOLANT (SOI) ET PLAQUETTE SOI
(JA) SOIウエーハの製造方法およびSOIウエーハ
Abstract:
(EN) Provided is an SOI wafer manufacturing method for growing an epitaxial layer on an SOI layer of the SOI wafer obtained by forming an oxide film and an SOI layer on a base wafer so as to increase the SOI layer thickness. The epitaxial growth is performed in such a manner that the reflectance of the surface in a wavelength region of a heating light at the epitaxial growth start of the SOI wafer for growing the epitaxial layer is in the range from 30% to 80%. Thus, it is possible to provide a method for manufacturing an SOI wafer of high quality having a small slip shifting.
(FR) La présente invention concerne un procédé de fabrication d’une plaquette SOI pour faire croître une couche épitaxique sur une couche SOI de la plaquette SOI obtenue en disposant une pellicule d'oxyde et une couche SOI sur une plaquette de base de façon à augmenter l'épaisseur de la couche SOI. La croissance épitaxique est réalisée de telle façon que le facteur de réflexion de la surface dans une zone de longueur d’onde d’une lumière chauffante au début de la croissance épitaxique de la plaquette SOI pour faire croître la couche épitaxique est comprise entre 30% et 80%. Il est ainsi possible d’obtenir un procédé de fabrication d’une plaquette SOI de haute qualité présentant un faible décalage de glissement.
(JA)  本発明は、ベースウエーハ上に酸化膜およびSOI層を形成したSOIウエーハのSOI層上にエピタキシャル層を成長させてSOI層を厚くするSOIウエーハの製造方法において、前記エピタキシャル層を成長させるSOIウエーハのエピタキシャル成長開始時の加熱光の波長域における表面の反射率が30%以上80%以下となるようにしてエピタキシャル成長を行うことを特徴とするSOIウエーハの製造方法である。これにより、ベースウエーハ上に酸化膜およびSOI層を形成したSOIウエーハのSOI層上にエピタキシャル層を成長させてSOI層を厚くするSOIウエーハの製造方法において、スリップ転位等の少ない高品質なSOIウエーハを製造する方法が提供される。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)