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1. (WO2007081642) FLASH DEVICEWITH SHARED WORD LINES AND MANUFACTURING METHODS THEREOF
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CLAIMS:

1. A method of forming a nonvolatile memory array on a substrate surface comprising:
forming a plurality of shallow trench isolation structures on a substrate, individual ones of the plurality of shallow trench isolation structures extending in a first direction, ones of the plurality of shallow trench isolation structures spaced apart in a second direction; and
subsequently forming a plurality continuous conductive strips, an individual continuous conductive strip including first, second, third and fourth conductive portions, the first conductive portion extending in the second direction and overlying the plurality of shallow trench isolation structures, the second conductive portion extending in the second direction and overlying the plurality of shallow trench isolation structures, the first and second conductive strips spaced apart in the first direction, the third and fourth conductive portions extending in the first direction to connect the first and second conductive portions.

2. The method of claim 1 wherein the individual conductive strip forms a closed rectangle, and the first, second, third and fourth conductive portions form the sides of the rectangle.

3. The method of claim 1 wherein the first conductive portion forms a first word line and the second conductive portion forms a second word line.

4. The method of claim 1 wherein a width of an individual one of the plurality of continuous conductive strips is established by spacers formed on sidewalls.

5. The method of claim 4 wherein the width is less than a minimum feature size of a lithographic process used to form the nonvolatile memory array.

6. The method of claim 5 wherein the spacers are slimmed to be less than the minimum feature size of the lithographic process used.

7. The method of claim 1 further comprising forming select gate lines that extend in the first direction, the select gate lines being at least as wide as the minimum feature size.

8. The method of claim 1 further comprising forming floating gates underlying the plurality of first conductive portions so that a first plurality of NAND strings is formed between the plurality of shallow trench isolation structures.

9. The method of claim 8 wherein the first plurality of NAND strings extend between a first select gate line and a second select gate line.

10. The method of claim 9 further comprising forming a first conductive shield plate that extends over the first plurality of NAND strings.

11. The method of claim 10 further comprising forming floating gates underlying the plurality of second conductive portions so that a second plurality of NAND strings is formed between the plurality of shallow trench isolation structures, the second plurality of NAND strings extending between a third select gate line and a fourth select gate line and a second conductive shield plate extending over the second plurality of NAND strings.

12. The method of claim 1 further comprising forming a conductive shield plate that extends between the plurality of continuous conductive strips.

13. A method of forming a nonvolatile memory array comprising:
forming a masking layer that includes a plurality of masking portions extending over a substrate;
forming a plurality of sidewall spacers along sidewalls of the plurality of masking portions;
forming a plurality of word lines extending across the nonvolatile memory array in a first direction and spaced apart in a second direction, the second direction being perpendicular to the first direction, individual word lines having a first width in the second direction that is less than a minimum feature size of a lithographic process used to form the nonvolatile memory array, the first width established by the width of a sidewall spacer of a plurality of sidewall spacers, an individual word line overlying floating gates of the nonvolatile memory array, individual ones of the plurality of word lines separated from adjacent ones of the plurality of word lines by a distance that is less than the minimum feature size produced by a lithographic process used to form the masking layer; and
forming a plurality of select gate lines extending across the nonvolatile memory array in the first direction, individual ones of the plurality of select gate lines having a second width that is at least as great as the minimum feature size, the second width established by the distance between two sidewall spacers of the plurality of sidewall spacers.

14. The method of claim 13 wherein individual word lines are linked in pairs by conductive elements extending in the second direction.

15. The method of claim 13 further comprising a conductive shield plate that extends between the plurality of word lines.

16. The method of claim 13 wherein the masking portions are formed by lithographically patterning a photoresist layer to form photoresist portions having a width that is equal to a minimum feature size and subsequently slimming the photoresist portions.

17. A method of operating a NAND flash memory array that has word lines of a first block connected to word lines of a second block, the first block and the second block sharing a plurality of bit lines, the first block having a first shield plate and the second block having a second shield plate, comprising:
erasing data in the first block while maintaining data in the second block by applying a first voltage to the first shield plate while applying a second voltage to the second shield plate.

18. The method of claim 17 further comprising maintaining a common voltage on the word lines of the first block and word lines of the second block during the erasing.

19. The method of claim 17 wherein a portion of the substrate underlying the first block and the second block is maintained at a third voltage during erasing, the third voltage being higher than the first or second voltages.

20. The method of claim 19 wherein the first voltage is approximately 5 volts, the second voltage is approximately 18 volts and the third voltage is approximately 20volts.

21. The method of claim 17 further comprising writing data in the first block while not writing data in the second block by turning on select transistors of the first block while turning off select transistors of the second block and applying
programming voltages to the plurality of bit lines.

22. The method of claim 21 further comprising maintaining the first shield plate and the second shield plate at the same voltage during the writing data in the first block.

23. The method of claim 17 further comprising reading data from the first block while not reading data from the second block by turning on select transistors of the first block while turning off select transistors of the second block and reading data through the plurality of bit lines.

24. The method of claim 23 further comprising maintaining the first shield plate and the second shield plate at the same voltage during the reading data from the first block.

25. A nonvolatile floating gate memory array comprising:
a first plurality of floating gate memory cells having a first plurality of word lines extending in a first direction;

a second plurality of floating gate memory cells having a second plurality of word lines extending in the first direction;
the first plurality of floating gate memory cells separated from the second plurality of memory cells in a second direction that is perpendicular to the first direction; and
the first plurality of word lines electrically connected to the second plurality of word lines by conductive portions extending in the second direction.

26. The nonvolatile floating gate memory array of claim 25 wherein the first plurality of word lines, the second plurality of word lines and the conductive portions form a plurality of concentric rectangles.

27. The nonvolatile floating gate memory array of claim 26 wherein individual ones of the first plurality of word lines and the second plurality of word lines have a width that is less than a minimum feature size that is produced by a lithographic process used to form the memory array.

28. The nonvolatile floating gate memory array of claim 25 further comprising select gate lines to separately select the first plurality of floating gate memory cells and the second plurality of floating gate memory cells.

29. The nonvolatile floating gate memory array of claim 25 further comprising a first shield plate overlying the first plurality of floating gate memory cells and a second shield plate overlying the second plurality of floating gate memory cells.

30. The nonvolatile floating gate memory array of claim 29 further comprising a first driver circuit connected to the first shield plate and a second driver circuit connected to the second shield plate.

31. The nonvolatile floating gate memory array of claim 25 wherein the first plurality of word lines and the second plurality of word lines share word line decoder and driver circuits.

32. A nonvolatile floating gate memory array comprising:
a first plurality of strings of floating gate memory cells, the first plurality of strings having a first source select line connecting source select gates of the first plurality of strings and having a first drain select line connecting drain select gates of the first plurality of strings;
a second plurality of strings of floating gate memory cells, the second plurality of strings having a second source select line connecting source select gates of the second plurality of strings and having a second drain select line connecting drain select gates of the second plurality of strings;
a plurality of conductive portions extending across the first plurality of strings to connect control gates of the first plurality of strings and extending across the second plurality of strings to connect control gates of the second plurality of strings; and
a plurality of bit lines shared by the first plurality of strings and the second plurality of strings so that an individual bit line of the plurality of bit lines connects to a string of the first plurality of strings and connects to a string of the second plurality of strings.

33. The nonvolatile floating gate memory array of claim 32 wherein the plurality of conductive portions form a plurality of concentric rectangles.

34. The nonvolatile floating gate memory array of claim 32 wherein individual ones of the plurality of conductive portions have a width that is less than a minimum feature size of a lithographic process used to form the memory array.

35. The nonvolatile floating gate memory array of claim 32 wherein the plurality of conductive portions are connected to driver circuits that are shared by the first plurality of strings and the second plurality of strings.

36. The nonvolatile floating gate memory array of claim 32 wherein applying voltages to erase data in the first plurality of strings of floating gate memory cells causes data in the second plurality of strings to be erased also.

37. The nonvolatile floating gate memory array of claim 32 wherein a first shield plate is capacitively coupled to floating gates of the first plurality of strings of floating gate memory cells and a second shield plate is capacitively coupled to floating gates of the second plurality of strings of floating gate memory cells, and wherein data is erased from the first plurality of strings of floating gate memory cells without erasing data from the second plurality of strings of floating gate memory cells by applying a first voltage to the first shield plate while applying a second voltage to the second shield plate.