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Machine translation
1. (WO2007078958) PERFORMING DIRECT CACHE ACCESS TRANSACTIONS BASED ON A MEMORY ACCESS DATA STRUCTURE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/078958    International Application No.:    PCT/US2006/048555
Publication Date: 12.07.2007 International Filing Date: 18.12.2006
IPC:
G06F 12/08 (2006.01), G06F 12/10 (2006.01), G06F 12/14 (2006.01)
Applicants: INTEL CORPORATION [US/US]; 2200 Mission College Boulevard, Santa Clara, CA 95052 (US) (For All Designated States Except US).
MADUKKARUMUKUMANA, Rajesh, Sankaran [IN/US]; (US) (For US Only).
MUTHRASANALLUR, Sridhar [IN/US]; (US) (For US Only).
HUGGAHALLI, Ramakrishna [US/US]; (US) (For US Only).
ILLIKKAL, Rameshkumar [IN/US]; (US) (For US Only)
Inventors: MADUKKARUMUKUMANA, Rajesh, Sankaran; (US).
MUTHRASANALLUR, Sridhar; (US).
HUGGAHALLI, Ramakrishna; (US).
ILLIKKAL, Rameshkumar; (US)
Agent: VINCENT, Lester, J.; BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, 12400 Wilshire Boulevard, 7th Floor, Los Angeles, CA 90025 (US)
Priority Data:
11/323,262 30.12.2005 US
Title (EN) PERFORMING DIRECT CACHE ACCESS TRANSACTIONS BASED ON A MEMORY ACCESS DATA STRUCTURE
(FR) EXECUTION DE TRANSACTIONS A MEMOIRE CACHE A ACCES DIRECT BASEE SUR UNE STRUCTURE DE DONNEES A ACCES MEMOIRE
Abstract: front page image
(EN)Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory access based on a memory access data structure. The transaction logic is to assign direct cache access attributes to a transaction based on the memory access data structure.
(FR)La présente invention concerne des modes de réalisation d'un appareil, d'un procédé et d'un système pour le codage de transactions à mémoire cache à accès direct basé sur une structure de données à accès mémoire. Dans un mode de réalisation, un appareil comprend une logique d'accès mémoire et une logique de transaction. La logique d'accès mémoire permet de déterminer si on peut autoriser un accès mémoire basé sur une structure de données d'accès mémoire. La logique de transaction permet d’assigner des attributs à mémoire cache à accès direct à une transaction en se basant sur la structure de données à accès mémoire.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)