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Machine translation
1. (WO2007078755) INTEGRATED CONFIGURATION, FLOW AND EXECUTION SYSTEM FOR SEMICONDUCTOR DEVICE EXPERIMENTAL FLOWS AND PRODUCTION FLOWS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/078755    International Application No.:    PCT/US2006/047491
Publication Date: 12.07.2007 International Filing Date: 11.12.2006
IPC:
G05B 19/042 (2006.01), G06Q 50/00 (2006.01), G06Q 10/00 (2006.01), G05B 15/02 (2006.01)
Applicants: INTEL CORPORATION [US/US]; 2200 Mission College Boulevard, Santa Clara, CA 95052 (US) (For All Designated States Except US).
WINSTEAD, Charles, H. [US/US]; (US) (For US Only).
SANKARAN, Rajshree, P. [US/US]; (US) (For US Only).
TAHA, Samer, M. [JO/US]; (US) (For US Only).
QU, Jiang [CN/US]; (US) (For US Only).
MOULI, Chandra [US/US]; (US) (For US Only)
Inventors: WINSTEAD, Charles, H.; (US).
SANKARAN, Rajshree, P.; (US).
TAHA, Samer, M.; (US).
QU, Jiang; (US).
MOULI, Chandra; (US)
Agent: VINCENT, Lester, J.; BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, 12400 Wilshire Boulevard, 7th Floor, Los Angeles, CA 90025 (US)
Priority Data:
11/325,926 30.12.2005 US
Title (EN) INTEGRATED CONFIGURATION, FLOW AND EXECUTION SYSTEM FOR SEMICONDUCTOR DEVICE EXPERIMENTAL FLOWS AND PRODUCTION FLOWS
(FR) CONFIGURATION INTÉGRÉE, SYSTÈME DE FLUX ET D'EXÉCUTION POUR FLUX EXPÉRIMENTAUX ET FLUX DE PRODUCTION DE DISPOSITIFS SEMI-CONDUCTEURS
Abstract: front page image
(EN)According to embodiments of the invention, an integrated configuration, flow and execution systems (ICFES) may be used to specify, control and record a history of processing of both semiconductor device experimental lots and production lots of wafers. Moreover, the system allows combining of one or more partial flows of pre-existing flow blocks, and special processing into another processing flow block. A lot plan can be created that includes the flow block, and the lot plan can be updated to include partial flows and special processing before or during processing of the lot plan.
(FR)Selon les modes de réalisation de l'invention, une configuration intégrée, des systèmes de flux et d'exécution (ICFES) peuvent être utilisés pour spécifier, commander et enregistrer un historique de traitement aussi bien de lots expérimentaux de dispositifs semi-conducteurs que de lots de productions de plaquettes. Le système permet en plus de combiner un flux partiel ou plus de blocs de flux préexistants et un traitement spécial dans un autre bloc de flux de traitement. Un plan de lots qui comprend le bloc de flux peut être créé, et le plan de lots peut être mis à jour pour incorporer les flux partiels et le traitement spécial avant ou pendant le traitement du plan de lots.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)