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Machine translation
1. (WO2007078724) METHOD AND SYSTEM FOR OPTIMIZING LATENCY OF DYNAMIC MEMORY SIZING
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/078724    International Application No.:    PCT/US2006/047364
Publication Date: 12.07.2007 International Filing Date: 11.12.2006
IPC:
G06F 12/08 (2006.01), G06F 12/12 (2006.01)
Applicants: INTEL CORPORATION [US/US]; 2200 Mission College Boulevard, Santa Clara, CA 95052 (US) (For All Designated States Except US).
JAHAGIRDAR, Sanjeev [IN/US]; (US) (For US Only)
Inventors: JAHAGIRDAR, Sanjeev; (US)
Agent: VINCENT, Lester, J.; Blakely, Sokoloff, Taylor & Zafman LLP, 12400 Wilshire Boulevard, 7th Floor, Los Angeles, CA 90025 (US)
Priority Data:
11/323,259 30.12.2005 US
Title (EN) METHOD AND SYSTEM FOR OPTIMIZING LATENCY OF DYNAMIC MEMORY SIZING
(FR) MÉTHODE ET SYSTÈME D’OPTIMISATION DE LA LATENCE DU DIMENSIONNEMENT DYNAMIQUE DE MÉMOIRE
Abstract: front page image
(EN)Some embodiments of the invention include a system and method for optimizing the latency of dynamic memory sizing. In some embodiments, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The latency of changes to the memory based on operating requirements is optimized by the method and system. Other embodiments are described.
(FR)Certains exemples de mode de réalisation de l’invention incluent un système et une méthode d’optimisation de la latence du dimensionnement dynamique de mémoire. Selon certains exemples de mode de réalisation, les exigences d’exploitation peuvent refléter la quantité de mémoire nécessaire pour réaliser des opérations comparables. Une logique de gestion de puissance mémoire est utilisée pour coordonner les exigences de mémoire et les exigences d’exploitation. La latence de changements de la mémoire basés sur les exigences d’exploitation est optimisée par la méthode et le système. D’autres exemples de mode de réalisation sont décrits.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)