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1. (WO2007074688) NITRIDE COMPOUND SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/074688    International Application No.:    PCT/JP2006/325335
Publication Date: 05.07.2007 International Filing Date: 20.12.2006
IPC:
H01S 5/02 (2006.01), H01L 21/205 (2006.01), H01L 21/301 (2006.01), H01S 5/323 (2006.01)
Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. [JP/JP]; 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501 (JP) (For All Designated States Except US).
HASEGAWA, Yoshiaki; (For US Only).
YOKOGAWA, Toshiya; (For US Only).
YAMADA, Atsushi; (For US Only).
MATSUDA, Yoshiaki; (For US Only)
Inventors: HASEGAWA, Yoshiaki; .
YOKOGAWA, Toshiya; .
YAMADA, Atsushi; .
MATSUDA, Yoshiaki;
Agent: OKUDA, Seiji; OKUDA & ASSOCIATES, 10th Floor Osaka Securities Exchange Bldg. 8-16, Kitahama 1-chome, Chuo-ku Osaka-shi, Osaka 5410041 (JP)
Priority Data:
2005-371863 26.12.2005 JP
Title (EN) NITRIDE COMPOUND SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME
(FR) ÉLÉMENT SEMI-CONDUCTEUR AVEC UN COMPOSÉ AU NITRURE ET SON PROCÉDÉ DE FABRICATION
(JA) 窒化化合物半導体素子およびその製造方法
Abstract: front page image
(EN)Provided is a method for manufacturing a nitride compound semiconductor element having a substrate and a laminated structure (40) supported on the upper plane of the substrate. A wafer (1) to be divided into separated substrates is prepared. A plurality of semiconductor layers constituting the laminated structure (40) is grown on the wafer (1). A cleavage plane of the laminated structure (40) is formed by cleaving the wafer (1) and the semiconductor layer. A plurality of spaces are arranged at positions whereupon the cleavage planes are to be formed in the laminated structure. Thus, cleavage is performed at an excellent yield.
(FR)La présente invention concerne un procédé de fabrication d’un élément semi-conducteur avec un composé au nitrure comportant un substrat et une structure stratifiée (40) supportée sur le plan supérieur du substrat. Une plaquette (1) à diviser en substrats séparés est préparée. Une pluralité de couches semi-conductrices constituant la structure stratifiée (40) croît sur la plaquette (1). Un plan de clivage de la structure stratifiée (40) est constitué en fendant la plaquette (1) et la couche semi-conductrice. Une pluralité d’espaces est disposée à des positions auxquelles les plans de clivage doivent être constitués dans la structure stratifiée. Le clivage est ainsi effectué avec un excellent rendement.
(JA) 本発明は、基板と、基板の上面に支持される積層構造40とを備えた窒化化合物半導体素子の製造方法であって、まず、個々の基板に分割されるべきウェハ1を用意する。積層構造40を構成する複数の半導体層をウェハ1上に成長させる。ウェハ1および半導体層をへき開することにより積層構造40のへき開面を形成する。本発明では、積層構造においてへき開面が形成されるべき位置に複数の空隙を配列しておく。こうして、へき開を歩留まり良く行なうことができる。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)