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1. WO2007041155 - MICROELECTRONIC PACKAGE HAVING MULTIPLE CONDUCTIVE PATHS THROUGH AN OPENING IN A SUPPORT SUBSTRATE

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Publication Number WO/2007/041155
Publication Date 12.04.2007
International Application No. PCT/US2006/037646
International Filing Date 26.09.2006
IPC
H01L 23/13 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
H01L 25/065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
CPC
H01L 2224/45015
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
4501Shape
45012Cross-sectional shape
45015being circular
H01L 2224/45144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
45144Gold (Au) as principal constituent
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
H01L 2224/49113
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
49of a plurality of wire connectors
491Disposition
4911the connectors being bonded to at least one common bonding area, e.g. daisy chain
49113the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
H01L 23/13
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • HECK, John [US]/[US] (UsOnly)
  • MA, Qing [US]/[US] (UsOnly)
Inventors
  • HECK, John
  • MA, Qing
Agents
  • VINCENT, Lester J.
Priority Data
11/240,75030.09.2005US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MICROELECTRONIC PACKAGE HAVING MULTIPLE CONDUCTIVE PATHS THROUGH AN OPENING IN A SUPPORT SUBSTRATE
(FR) BOITIERS DE MICRO-ELECTRONIQUE A PLUSIEURS CONDUCTEURS TRAVERSANT UNE OUVERTURE PRATIQUEE DANS UN SUBSTRAT SUPPORT
front page image
Abstract
(EN)
Microelectronic packages are disclosed. A microelectronic package may include a substrate having first and second sides. Passive components may be located on the first side of the substrate. Interconnects may also be located on the first side of the substrate, and may be electrically coupled with the passive components. Microelectronic components may be located on the first side of the substrate and may be electrically coupled with interconnects. The substrate may include an opening therein. The opening may lead from the second side of the substrate toward the first side of the substrate. A plurality of conductive paths may be at least partially included in the opening. Each of the conductive paths may lead from the second side of the substrate toward the first side of the substrate to communicate electrical signals to interconnects. Methods of making the packages and electronic devices including the packages are also disclosed.
(FR)
L'invention porte sur des boîtiers de micro-électronique pouvant comporter un substrat à double face où les composants passifs sont situés d'un premier côté et les interconnexions, également situées du premier côté, peuvent être reliées électriquement aux composants passifs. Les composants microélectroniques également situées du premier côté, peuvent aussi être reliées électriquement aux interconnexions. Le substrat peut par ailleurs comporter une ouverture reliant le premier côté au deuxième, et dans laquelle passent au moins en partie plusieurs conducteurs communiquant des signaux électriques aux interconnexions. L'invention porte en outre sur un procédé de réalisation de boîtiers, et sur des dispositifs électroniques les comprenant.
Also published as
EP06815559
EP6815559
US20070077747
Latest bibliographic data on file with the International Bureau
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