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1. WO2007036050 - MEMORY WITH OUTPUT CONTROL

Publication Number WO/2007/036050
Publication Date 05.04.2007
International Application No. PCT/CA2006/001609
International Filing Date 29.09.2006
IPC
G11C 11/4197 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
4193Auxiliary circuits specific to particular types of semiconductor storage devices, e.g. for addressing, driving, sensing, timing, power supply, signal propagation
4197Read-write circuits
G11C 11/4093 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4093Input/output data interface arrangements, e.g. data buffers
G11C 11/4063 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
G11C 16/26 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
26Sensing or reading circuits; Data output circuits
CPC
G06F 1/12
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
12Synchronisation of different clock signals ; provided by a plurality of clock generators
G11C 11/5628
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5628Programming or writing circuits; Data input circuits
G11C 11/5642
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5642Sensing or reading circuits; Data output circuits
G11C 16/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
G11C 16/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 16/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
14Circuits for erasing electrically, e.g. erase voltage switching circuits
16for erasing blocks, e.g. arrays, words, groups
Applicants
  • MOSAID TECHNOLOGIES INCORPORATED [CA]/[CA] (AllExceptUS)
  • OH, HakJune [CA]/[CA] (UsOnly)
  • PYEON, Hong, Beom [CA]/[CA] (UsOnly)
  • KIM, Jin-Ki [CA]/[CA] (UsOnly)
Inventors
  • OH, HakJune
  • PYEON, Hong, Beom
  • KIM, Jin-Ki
Agents
  • KINSMAN, L. Anne
Priority Data
11/324,02330.12.2005US
60/722,36830.09.2005US
60/847,79027.09.2006US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY WITH OUTPUT CONTROL
(FR) MEMOIRE A CONTROLE DES SORTIES
Abstract
(EN)
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
(FR)
La présente invention concerne un appareil, un système et un procédé pour contrôler un transfert de données vers un port de sortie d'une interface de liaison de données en série dans une mémoire à semi-conducteur. Dans un exemple, un dispositif de mémoire flash peut présenter de multiples liaisons de données en série, de multiples banques de mémoire et des ports d'entrée de contrôle qui permettent au dispositif de mémoire de transférer les données en série vers un port de sortie de données en série du dispositif de mémoire. Dans un autre exemple, un dispositif de mémoire flash peut présenter une seule liaison de données en série, une seule banque de mémoire, un port d'entrée de données en série, ainsi qu'un port d'entrée de contrôle permettant de recevoir des signaux d'activation de sortie. Les dispositifs de mémoire flash peuvent être montés en cascade selon une configuration en guirlande, en utilisant des lignes à signaux d'écho, afin d'établir une communication en série entre des dispositifs de mémoire.
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