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1. WO2007036020 - SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CURRENT LEAKAGE REDUCTION SCHEME

Publication Number WO/2007/036020
Publication Date 05.04.2007
International Application No. PCT/CA2006/001417
International Filing Date 29.08.2006
IPC
G05F 1/10 2006.01
GPHYSICS
05CONTROLLING; REGULATING
FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
1Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
10Regulating voltage or current
H01L 23/58 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 27/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H03K 17/14 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and -breaking
14Modifications for compensating variations of physical values, e.g. of temperature
H03K 19/0948 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
08using semiconductor devices
094using field-effect transistors
0944using MOSFET
0948using CMOS
CPC
H01L 27/092
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
092complementary MIS field-effect transistors
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H03K 19/0016
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0008Arrangements for reducing power consumption
0016by using a control or a clock signal, e.g. in order to apply power supply
Applicants
  • MOSAID TECHNOLOGIES INCORPORATED [CA]/[CA] (AllExceptUS)
  • OH, HakJune [CA]/[CA] (UsOnly)
Inventors
  • OH, HakJune
Agents
  • HUNG, Shin
Priority Data
11/238,97530.09.2005US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CURRENT LEAKAGE REDUCTION SCHEME
(FR) CIRCUIT INTEGRE A SEMI-CONDUCTEUR QUI PRESENTE UN PLAN DE REDUCTION DE FUITE DE COURANT
Abstract
(EN)
A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor. The power gating to the CMOS inverter is performed by feedback of the output signal and the complementary input signal, with the result that current leakage reduction through the CMOS controlled inverter is achieved. A self leakage reduction with power gating transistors is applicable to another type of logic gates such as NAND, NOR and Exclusive-OR, AND, OR.
(FR)
La présente invention concerne un circuit intégré à semi-conducteur comprenant un inverseur contrôlé par CMOS qui est constitué de transistors PMOS et NMOS connectés en série. La source du transistor NMOS est couplée à une ligne de terre par l'intermédiaire d'un transistor NMOS supplémentaire afin de portillonner le courant (« power gating ») d'une tension VSS. La source du transistor PMOS peut être couplée à une ligne d'alimentation en courant par l'intermédiaire d'un transistor PMOS supplémentaire afin de portillonner le courant d'une tension VDD. L'inverseur reçoit un signal d'entrée IN et sa version complémentaire qui a transité plus tôt que le signal d'entrée. En réponse au signal d'entrée, l'inverseur produit un signal de sortie. Une porte NON-ET qui reçoit le signal de sortie et le signal d'entrée complémentaire commande le transistor NMOS de portillonnage de courant. Une porte NON-OU qui reçoit le signal de sortie et le signal d'entrée complémentaire commande le transistor PMOS de portillonnage de courant. Le portillonnage de courant sur l'inverseur CMOS est réalisé par rétroaction du signal de sortie et du signal d'entrée complémentaire, ce qui résulte en une réduction de la fuite de courant grâce à l'inverseur contrôlé par CMOS. Une réduction de fuite automatique avec des transistors de portillonnage de courant peut s'appliquer à un autre type de portes logiques, telles que NON-ET, NON-OU et OU exclusif, ET, OU.
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