WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2007022491) INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/022491    International Application No.:    PCT/US2006/032551
Publication Date: 22.02.2007 International Filing Date: 16.08.2006
IPC:
H03K 19/003 (2006.01)
Applicants: NOVELICS [US/US]; 120 Vantis, Suite 460, Aliso Viejo, CA 92656 (US) (For All Designated States Except US).
AFGHAHI, Morteza [US/US]; (US) (For US Only).
TERZIOGLU, Esin [CY/US]; (US) (For US Only).
WINOGRAD, Gil, I. [US/US]; (US) (For US Only)
Inventors: AFGHAHI, Morteza; (US).
TERZIOGLU, Esin; (US).
WINOGRAD, Gil, I.; (US)
Agent: HALLMAN, Jonathan, W.; Macpherson Kwok Chen & Heid LLP, 2033 Gateway Place, Suite 400, San Jose, CA 95110 (US)
Priority Data:
60/708,729 16.08.2005 US
11/301,236 12.12.2005 US
Title (EN) INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT
(FR) CIRCUITS INTEGRES A COURANT DE FUITE REDUIT
Abstract: front page image
(EN)In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.
(FR)Dans une forme d'exécution, des transistors NMOS ont leurs sources couplées à un noeud source commun, de sorte que les transistors NMOS transmettent un courant de fuite si le noeud source commun est à la masse. En vue de réduire ce courant de fuite, le noeud source commun est augmenté en potentiel. De façon similaire, des transistors PMOS ont leurs sources couplées à un noeud source commun, de sorte que les transistors PMOS transmettent un courant de fuite si le noeud source commun est chargé à une tension d'alimentation VDD. En vue de réduire ce courant de fuite, le noeud source commun est abaissé en potentiel.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)