WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2007019003) INCREASING WORKLOAD PERFORMANCE OF ONE OR MORE CORES ON MULTIPLE CORE PROCESSORS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/019003    International Application No.:    PCT/US2006/028199
Publication Date: 15.02.2007 International Filing Date: 20.07.2006
Chapter 2 Demand Filed:    25.06.2007    
IPC:
G06F 1/32 (2006.01)
Applicants: ADVANCED MICRO DEVICES, INC. [US/US]; ONE AMD PLACE, MAIL STOP 68, P.O. Box 3453, Sunnyvale, CA 94088-3453 (US) (For All Designated States Except US).
CLARK, Michael, T. [US/US]; (US) (For US Only)
Inventors: CLARK, Michael, T.; (US)
Agent: DRAKE, Paul, S.; ADVANCED MICRO DEVICES, INC., 5204 EAST BEN WHITE BOULEVARD, Mail Stop 562, Austin, TX 78741 (US).
BROOKES BATCHELLOR LLP; 102-108 Clerkenwell Road, London EC1M 5SA (GB)
Priority Data:
11/195,305 02.08.2005 US
Title (EN) INCREASING WORKLOAD PERFORMANCE OF ONE OR MORE CORES ON MULTIPLE CORE PROCESSORS
(FR) AUGMENTATION DE LA PUISSANCE D'AU MOINS UN COEUR DE PROCESSEURS MULTI-COEURS
Abstract: front page image
(EN)A processing node (12) that is integrated onto a single integrated circuit chip includes a first processor core (18A) and a second processor core (18B). The processing node also includes an operating system (13A, 13B) executing on either of the first processor core and the second processor core. The operating system may monitor a current utilization of the first processor core and the second processor core. The operating system may cause the first processor core to operate at performance level that is lower than a system maximum performance level and the second processor core to operate at performance level that is higher than the system maximum performance level in response to detecting the first processor core operating below a utilization threshold.
(FR)La présente invention concerne un noeud de traitement (12) intégré en un seul microcircuit et comportant deux coeurs de processeur (18A, 18B). Le noeud de traitement comporte également un système d'exploitation (13A, 13B) tournant indifféremment sur l'un ou l'autre des coeurs. Le système d'exploitation surveille l'utilisation courante des deux coeurs. Il peut ainsi amener le premier coeur à travailler à un niveau de puissance inférieur au maximum du système, le second coeur passant à un niveau supérieur au niveau maximum du système dans la mesure où le système d'exploitation a détecté que le premier coeur travaille en dessous d'un plafond d'utilisation.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)