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Machine translation
1. (WO2007016047) METHOD AND STRUCTURE FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/016047    International Application No.:    PCT/US2006/028718
Publication Date: 08.02.2007 International Filing Date: 24.07.2006
IPC:
H01L 29/76 (2006.01), H01L 29/94 (2006.01), H01L 31/062 (2006.01), H01L 31/113 (2006.01), H01L 31/119 (2006.01)
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road, Armonk, NY 10504 (US) (For All Designated States Except US).
GAIDIS, Michael, C. [US/US]; (US) (For US Only).
RADENS, Carl [US/US]; (US) (For US Only).
CLEVENGER, Lawrence, A. [US/US]; (US) (For US Only).
DALTON, Timothy, J. [US/US]; (US) (For US Only).
HSU, Louis, L.c. [US/US]; (US) (For US Only).
WONG, Keith Kwong Hon [US/US]; (US) (For US Only).
YANG, Chih-Chao [--/US]; (US) (For US Only)
Inventors: GAIDIS, Michael, C.; (US).
RADENS, Carl; (US).
CLEVENGER, Lawrence, A.; (US).
DALTON, Timothy, J.; (US).
HSU, Louis, L.c.; (US).
WONG, Keith Kwong Hon; (US).
YANG, Chih-Chao; (US)
Agent: SULLIVAN, Sean, F.; CANTOR COLBURN LLP, 55 Griffin Road South, Bloomfield, CT 06002 (US)
Priority Data:
11/193,660 29.07.2005 US
Title (EN) METHOD AND STRUCTURE FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES
(FR) PROCEDE ET STRUCTURE POUR FORMER UNE LIGNE DE BITS A TRANCHEE D'INTERCONNEXION POUR DISPOSITIFS DE MEMOIRE MRAM
Abstract: front page image
(EN)A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
(FR)L'invention concerne un dispositif de mémoire vive magnétique (MRAM) qui comprend un empilement de jonctions magnétiques à effet tunnel (MTJ) formées sur une couche inférieure de câblage, un masque dur formé sur l'empilement MTJ, et une couche supérieure de câblage formée sur le masque dur. Une ligne de bits à tranchée d'interconnexion est formée dans la couche supérieure de câblage, ladite ligne de bits étant en contact avec le masque dur et avec une couche d'arrêt de gravure qui entoure partiellement les parois latérales du masque dur.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)