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Machine translation
1. (WO2007011853) LOW INDUCTANCE MULTILAYER CAPACITOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/011853    International Application No.:    PCT/US2006/027635
Publication Date: 25.01.2007 International Filing Date: 17.07.2006
IPC:
H01G 4/005 (2006.01), H01G 4/228 (2006.01), H01G 4/06 (2006.01)
Applicants: ROY, Apurba [US/US]; (US)
Inventors: ROY, Apurba; (US)
Agent: BOOKS, Mark E.; Polster, Lieder, Woodruff & Lucchesi, L.C., 12412 Powerscourt Drive, St. Louis, MO 63131 (US)
Priority Data:
60/700,642 19.07.2005 US
Title (EN) LOW INDUCTANCE MULTILAYER CAPACITOR
(FR) CONDENSATEUR MULTICOUCHE A FAIBLE INDUCTANCE
Abstract: front page image
(EN)A multilayer parallel plate capacitor with an extremely low inductance comprises a generally rectangular parallelepiped that includes at least one pair of generally rectangular consecutive composite layers (40A, 40B) stacked parallel to each other in the vertical direction, each composite layer (40A, 40B) of the pair comprising a dielectric substrate (41A, 41B) and a conductor plate (42A, 42B) thereon. Each conductor plate (42A, 42B) includes two or more lead portions (45A, 45B) to enable connection to terminal electrodes, and plates (42A, 42B) on consecutive composite layers (40A, 40B) are connected to terminal electrodes of opposite polarity. Each conductor plate (42A, 42B) advantageously includes one or more non-conductive regions comprising slots (44Y) in the transverse direction, and one or more non-conductive regions comprising slots (44X) in the longitudinal direction. These slots (44X, 44Y) provide directionality to the electrical currents (47A, 47B) through the plates (42A, 42B), resulting in a capacitor structure with greatly reduced inductance.
(FR)L'invention concerne un condensateur multicouche à plaques parallèles à inductance extrêmement faible d'une forme généralement parallélépipédique rectangulaire, qui comporte au moins une paire de couches composites consécutives généralement rectangulaires (40A, 40B) empilées parallèles verticalement, chaque couche composite (40A, 40B) comprenant un substrat diélectrique (41A, 41B) sur lequel est posée une plaque conductrice (42A, 42B). Chaque plaque conductrice (42A, 42B) comporte une ou plusieurs parties fils (46A, 46B) permettant d'activer une connexion aux terminaisons, et les plaques (42A, 42B) sur les couches composites consécutives (40A, 40B) sont reliées aux terminaisons de polarité opposée. Chaque plaque conductrice (42A, 42B) comporte avantageusement une ou plusieurs zones non conductrices, comprenant des fentes (44), qui fournissent une directionalité aux courants (47A, 47B) à travers les plaques (42A, 42B), le résultat étant une structure de condensateur à inductance considérablement réduite.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)