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1. (WO2007011789) SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE BETWEEN AT LEAST ONE PAIR OF SPACED APART STRESS REGIONS AND ASSOCIATED METHODS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2007/011789    International Application No.:    PCT/US2006/027503
Publication Date: 25.01.2007 International Filing Date: 14.07.2006
Chapter 2 Demand Filed:    15.05.2007    
IPC:
H01L 29/15 (2006.01), H01L 29/10 (2006.01), H01L 21/336 (2006.01), H01L 21/8234 (2006.01)
Applicants: MEARS TECHNOLOGIES, INC. [US/US]; 1100 Winter Street, Suite 4700, Waltham, MA 02451 (US) (For All Designated States Except US).
MEARS, Robert, J. [GB/US]; (US) (For US Only).
KREPS, Scott, A. [US/US]; (US) (For US Only)
Inventors: MEARS, Robert, J.; (US).
KREPS, Scott, A.; (US)
Agent: REGAN, Christopher F.; Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A., 255 S. Orange Ave, Suite 1401, Orlando, FL 32801 (US)
Priority Data:
60/699,949 15.07.2005 US
11/457,269 13.07.2006 US
11/457,276 13.07.2006 US
Title (EN) SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE BETWEEN AT LEAST ONE PAIR OF SPACED APART STRESS REGIONS AND ASSOCIATED METHODS
(FR) DISPOSITIF A SEMI-CONDUCTEUR COMPRENANT UNE COUCHE A HETEROSTRUCTURE CONTRAINTE ENTRE AU MOINS UNE PAIRE DE ZONES DE CONTRAINTE ESPACEES ET PROCEDES ASSOCIES
Abstract: front page image
(EN)A semiconductor device may include at least one pair of spaced apart stress regions (227, 228) , and a strained superlattice layer (225) between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers . Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions .
(FR)La présente invention concerne un dispositif à semi-conducteur pouvant comprendre au moins une paire de zones de contrainte espacées (227, 228) et une couche à hétérostructure contrainte (225) dotée d'une pluralité de groupes de couches superposés qui se trouve entre ces zones. Chaque groupe de couches de la couche à hétérostructure contrainte peut comporter une pluralité de monocouches semi-conductrices de base superposées définissant une section semi-conductrice de base, et au moins une monocouche non semi-conductrice contrainte au sein d'un réseau cristallin de sections semi-conductrices de base adjacentes.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)