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1. (WO2007011627) SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE LAYER ABOVE A STRESS LAYER AND ASSOCIATED METHODS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/011627 International Application No.: PCT/US2006/027119
Publication Date: 25.01.2007 International Filing Date: 14.07.2006
Chapter 2 Demand Filed: 15.05.2007
IPC:
H01L 29/15 (2006.01) ,H01L 29/10 (2006.01) ,H01L 21/8234 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
15
Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
Applicants:
MEARS Technologies, Inc. [US/US]; 1100 Winter Street Suite 4700 Waltham, Massachusetts 02451, US (AllExceptUS)
MEARS, Robert J. [GB/US]; US (UsOnly)
KREPS, Scott A. [US/US]; US (UsOnly)
Inventors:
MEARS, Robert J.; US
KREPS, Scott A.; US
Agent:
REGAN, Christopher F. ; 255 S. Orange Ave Suite 1401 Orlando, Florida 32802-3791, US
Priority Data:
11/457,25613.07.2006US
11/457,26313.07.2006US
60/699,94915.07.2005US
Title (EN) SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE LAYER ABOVE A STRESS LAYER AND ASSOCIATED METHODS
(FR) DISPOSITIF À SEMI-CONDUCTEUR COMPRENANT UNE COUCHE À HÉTÉROSTRUCTURE CONTRAINTE SUR UNE COUCHE DE CONTRAINTE ET PROCÉDÉS ASSOCIÉS
Abstract:
(EN) A semiconductor device may include a stress layer (26') and a strained superlattice layer (425') above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
(FR) La présente invention concerne un dispositif à semi-conducteur pouvant comprendre une couche de contrainte (26') recouverte d’une couche à hétérostructure contrainte (425') dotée d’une pluralité de groupes de couches superposés. Plus particulièrement, chaque groupe de couches de la couche à hétérostructure contrainte peut comporter une pluralité de monocouches semi-conductrices de base superposées définissant une section semi-conductrice de base, et au moins une monocouche non semi-conductrice contrainte au sein d’un réseau cristallin de sections semi-conductrices de base adjacentes.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1905090JP2009500870CN101253632CA2612118AU2006270323