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1. (WO2007011582) HIGH DENSITY NAND NON-VOLATILE MEMORY DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/011582 International Application No.: PCT/US2006/026894
Publication Date: 25.01.2007 International Filing Date: 12.07.2006
Chapter 2 Demand Filed: 14.02.2007
IPC:
H01L 27/115 (2006.01) ,H01L 21/8247 (2006.01) ,H01L 21/8246 (2006.01) ,G11C 16/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
8247
electrically-programmable (EPROM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
04
using variable threshold transistors, e.g. FAMOS
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 So. Federal Way Boise, ID 83716, US (AllExceptUS)
BHATTACHARYYA, Arup [US/US]; US (UsOnly)
Inventors:
BHATTACHARYYA, Arup; US
Agent:
WALSETH, Andrew, C.; Leffert, Jay & Polglaze, P.A. P.O. Box 581009 Minneapolis, MN 55458-1009, US
Priority Data:
11/181,34514.07.2005US
Title (EN) HIGH DENSITY NAND NON-VOLATILE MEMORY DEVICE
(FR) DISPOSITIF DE MEMOIRE NON VOLATILE NON-ET A HAUTE DENSITE
Abstract:
(EN) Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non- volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate- stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.
(FR) dispositifs et ensembles non volatiles reposant sur l'emploi de cellules de mémoire non volatile à double grille (ou grille arrière) avec des empilement de grilles à interbandes disposés au-dessus et au-dessous de la région de canal dans les configurations à piégeage de charge frontal ou arrière dans les architectures d'ensembles de mémoire NON-ET. Dans les modes de réalisation de la présente invention, les empilements de grilles à écart entre bandes avec barrières à effet tunnel asymétriques ou directes des cellules mémoires à noeuds flottants permettent une programmation tunnel et un effacement efficace avec des électrons et des trous tout en maintenant des barrières de blocage pour fortes charges et des sites de piégeage de vecteurs profond pour une bonne rétention de la charge. L'architecture des cellules de mémoire permet d'utiliser des dispositifs ou des ensembles mémoire de forte densité avec des lignes de mots à caractéristiques réduites et des grilles de sélections verticales.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080027946EP1908108JP2009501449CN101223640