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1. (WO2007011566) SEMICONDUCTOR CONSTRUCTIONS, MEMORY ARRAYS, ELECTRONIC SYSTEMS, AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2007/011566 International Application No.: PCT/US2006/026692
Publication Date: 25.01.2007 International Filing Date: 10.07.2006
Chapter 2 Demand Filed: 21.02.2007
IPC:
H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way Boise, ID 83716, US (AllExceptUS)
Inventors:
SANDHU, Gurtej, S.; US
DURCAN, D., Mark; US
Agent:
LATWESEN, David, G.; Wells, St. John P.S. 601 West First Avenue Suite 1300 Spokane, WA 99201, US
KENADY, Brent, D.; Wells St. John, P.S. 601 West First Avenue Suite 1300 Spokane, WA 99201-3828, US
Priority Data:
11/185,18619.07.2005US
Title (EN) SEMICONDUCTOR CONSTRUCTIONS, MEMORY ARRAYS, ELECTRONIC SYSTEMS, AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
(FR) STRUCTURES SEMI-CONDUCTRICES, MATRICES MEMOIRE, SYSTEMES ELECTRONIQUES ET PROCEDES POUR REALISER DES STRUCTURES SEMI-CONDUCTRICES
Abstract:
(EN) The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
(FR) L'invention concerne des structures semi-conductrices présentant des régions d'isolement à tranchées. Les tranchées des régions d'isolement à tranchées peuvent présenter des parties inférieures étroites et des parties supérieures larges situées au-dessus des parties inférieures. Un matériau isolant électrique peut remplir les parties supérieures larges tout en laissant des vides dans les parties inférieures étroites. Les parties inférieures peuvent avoir des parois latérales pratiquement verticales et peuvent se raccorder aux parties supérieures par des échelons s'étendant pratiquement perpendiculairement aux parois latérales. Les régions d'isolement à tranchées peuvent être intégrées dans une matrice mémoire et/ou dans un système électronique. L'invention concerne également des procédés pour la réalisation de structures semi-conductrices.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020080015948EP1911083JP2009503814CN101253617KR1020100120316